From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D426BC433F5 for ; Tue, 1 Feb 2022 20:41:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239503AbiBAUlx (ORCPT ); Tue, 1 Feb 2022 15:41:53 -0500 Received: from mga05.intel.com ([192.55.52.43]:16566 "EHLO mga05.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242605AbiBAUlg (ORCPT ); Tue, 1 Feb 2022 15:41:36 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1643748096; x=1675284096; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=cYIMGUOGguhuK47XvSH8cnFRT5RbfH0aDKi43vCctr4=; b=n/QYOUdJjdgtnWYvc6dVrmtNPnlObhU0ZOLvvM383uPzMpJ19U21Jo3+ Br6KdzVnV9kAV7MGA8KEcIChYcsvcrjD6ZCyXC3ihrzQkJHRZQFLrWKLS 0yBrWSy9fyN5tXlHGK++jPoK6/E8NI7Bp6W678FhyqXRWeKHSLaRWzIOx vjsnhSddaCQGD1wDo46vKAysEFRbLwmNmun+ZE//qz0/WC+N64ILbkCwb gL5+8mwK2p8xYDjIGgRoeE+WRQvy+24KcM+fxcAZ13Hty7j1WN08w4Dgg QDea0OH1+zRRgJDSLOApCHZ8DIV0mUuBrEgWgQhmJlttL/NS7q4N0Uzyp A==; X-IronPort-AV: E=McAfee;i="6200,9189,10245"; a="334143899" X-IronPort-AV: E=Sophos;i="5.88,334,1635231600"; d="scan'208";a="334143899" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Feb 2022 12:39:14 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,334,1635231600"; d="scan'208";a="479820826" Received: from bwalker-desk.ch.intel.com ([143.182.137.151]) by orsmga003.jf.intel.com with ESMTP; 01 Feb 2022 12:39:13 -0800 From: Ben Walker To: vkoul@kernel.org Cc: dmaengine@vger.kernel.org, dave.jiang@intel.com, Ben Walker Subject: [RESEND 10/10] dmaengine: Revert "cookie bypass for out of order completion" Date: Tue, 1 Feb 2022 13:38:13 -0700 Message-Id: <20220201203813.3951461-11-benjamin.walker@intel.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220201203813.3951461-1-benjamin.walker@intel.com> References: <20220201203813.3951461-1-benjamin.walker@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org This reverts commit 47ec7f09bc107720905c96bc37771e4ed1ff0aed. This is no longer necessary now that all assumptions about the order of completions have been removed from the dmaengine client API. Signed-off-by: Ben Walker --- .../driver-api/dmaengine/provider.rst | 19 ------------------- drivers/dma/dmatest.c | 11 +---------- drivers/dma/idxd/dma.c | 1 - include/linux/dmaengine.h | 2 -- 4 files changed, 1 insertion(+), 32 deletions(-) diff --git a/Documentation/driver-api/dmaengine/provider.rst b/Documentation/driver-api/dmaengine/provider.rst index 7c8ace703c96f..5bb4738ece0c2 100644 --- a/Documentation/driver-api/dmaengine/provider.rst +++ b/Documentation/driver-api/dmaengine/provider.rst @@ -262,22 +262,6 @@ Currently, the types available are: want to transfer a portion of uncompressed data directly to the display to print it -- DMA_COMPLETION_NO_ORDER - - - The device does not support in order completion. - - - The driver should return DMA_OUT_OF_ORDER for device_tx_status if - the device is setting this capability. - - - All cookie tracking and checking API should be treated as invalid if - the device exports this capability. - - - At this point, this is incompatible with polling option for dmatest. - - - If this cap is set, the user is recommended to provide an unique - identifier for each descriptor sent to the DMA device in order to - properly track the completion. - - DMA_REPEAT - The device supports repeated transfers. A repeated transfer, indicated by @@ -461,9 +445,6 @@ supported. - In the case of a cyclic transfer, it should only take into account the current period. - - Should return DMA_OUT_OF_ORDER if the device does not support in order - completion and is completing the operation out of order. - - This function can be called in an interrupt context. - device_config diff --git a/drivers/dma/dmatest.c b/drivers/dma/dmatest.c index 0574090a80c8c..f8cbeeaf8ed03 100644 --- a/drivers/dma/dmatest.c +++ b/drivers/dma/dmatest.c @@ -839,10 +839,7 @@ static int dmatest_func(void *data) result("test timed out", total_tests, src->off, dst->off, len, 0); goto error_unmap_continue; - } else if (status != DMA_COMPLETE && - !(dma_has_cap(DMA_COMPLETION_NO_ORDER, - dev->cap_mask) && - status == DMA_OUT_OF_ORDER)) { + } else if (status != DMA_COMPLETE) { result(status == DMA_ERROR ? "completion error status" : "completion busy status", total_tests, src->off, @@ -1020,12 +1017,6 @@ static int dmatest_add_channel(struct dmatest_info *info, dtc->chan = chan; INIT_LIST_HEAD(&dtc->threads); - if (dma_has_cap(DMA_COMPLETION_NO_ORDER, dma_dev->cap_mask) && - info->params.polled) { - info->params.polled = false; - pr_warn("DMA_COMPLETION_NO_ORDER, polled disabled\n"); - } - if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) { if (dmatest == 0) { cnt = dmatest_add_threads(info, dtc, DMA_MEMCPY); diff --git a/drivers/dma/idxd/dma.c b/drivers/dma/idxd/dma.c index 15bd87c2811e4..3400f49ca3c95 100644 --- a/drivers/dma/idxd/dma.c +++ b/drivers/dma/idxd/dma.c @@ -296,7 +296,6 @@ int idxd_register_dma_device(struct idxd_device *idxd) dma->dev = dev; dma_cap_set(DMA_PRIVATE, dma->cap_mask); - dma_cap_set(DMA_COMPLETION_NO_ORDER, dma->cap_mask); dma->device_release = idxd_dma_release; if (idxd->hw.opcap.bits[0] & IDXD_OPCAP_MEMMOVE) { diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h index 3c545b42723ec..47b0f0db1ef77 100644 --- a/include/linux/dmaengine.h +++ b/include/linux/dmaengine.h @@ -39,7 +39,6 @@ enum dma_status { DMA_IN_PROGRESS, DMA_PAUSED, DMA_ERROR, - DMA_OUT_OF_ORDER, }; /** @@ -63,7 +62,6 @@ enum dma_transaction_type { DMA_SLAVE, DMA_CYCLIC, DMA_INTERLEAVE, - DMA_COMPLETION_NO_ORDER, DMA_REPEAT, DMA_LOAD_EOT, /* last transaction type for creation of the capabilities mask */ -- 2.33.1