[PATCH v5 8/9] dmaengine: dw-edma: Add DW_EDMA_CHIP_32BIT_DBI for chip specific flags

Frank Li
2022-03-10T19:25:52Z

DW_EDMA_CHIP_32BIT_DBI was used by the controller drivers like i.MX8 that
allows only 32bit access to the DBI region.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
New patch at v5
- fix kernel test robot build error

drivers/dma/dw-edma/dw-edma-v0-core.c | 13 ++++++++-----
include/linux/dma/edma.h | 4 ++++
2 files changed, 12 insertions(+), 5 deletions(-)

diff --git a/drivers/dma/dw-edma/dw-edma-v0-core.c b/drivers/dma/dw-edma/dw-edma-v0-core.c
index 30686bfe1790c..013d9a9cb991e 100644
--- a/drivers/dma/dw-edma/dw-edma-v0-core.c
+++ b/drivers/dma/dw-edma/dw-edma-v0-core.c
@@ -417,15 +417,18 @@ void dw_edma_v0_core_start(struct dw_edma_chunk *chunk, bool first)
SET_CH_32(dw, chan->dir, chan->id, ch_control1,
(DW_EDMA_V0_CCS | DW_EDMA_V0_LLE));
/* Linked list */
- #ifdef CONFIG_64BIT
- SET_CH_64(dw, chan->dir, chan->id, llp.reg,
- chunk->ll_region.paddr);
- #else /* CONFIG_64BIT */
+ if ((chan->dw->chip->flags & DW_EDMA_CHIP_32BIT_DBI) ||
+ !IS_ENABLED(CONFIG_64BIT)) {
SET_CH_32(dw, chan->dir, chan->id, llp.lsb,
lower_32_bits(chunk->ll_region.paddr));
SET_CH_32(dw, chan->dir, chan->id, llp.msb,
upper_32_bits(chunk->ll_region.paddr));
- #endif /* CONFIG_64BIT */
+ } else {
+ #ifdef CONFIG_64BIT
+ SET_CH_64(dw, chan->dir, chan->id, llp.reg,
+ chunk->ll_region.paddr);
+ #endif
+ }
}
/* Doorbell */
SET_RW_32(dw, chan->dir, doorbell,
diff --git a/include/linux/dma/edma.h b/include/linux/dma/edma.h
index 5816c8bdf9a64..8897f8a79b521 100644
--- a/include/linux/dma/edma.h
+++ b/include/linux/dma/edma.h
@@ -36,6 +36,9 @@ enum dw_edma_map_format {
/* Probe EDMA engine locally and prevent generate MSI to host side*/
#define DW_EDMA_CHIP_LOCAL BIT(0)

+/* Only support 32bit DBI register access */
+#define DW_EDMA_CHIP_32BIT_DBI BIT(1)
+
/**
* struct dw_edma_chip - representation of DesignWare eDMA controller hardware
* @dev: struct device of the eDMA controller
@@ -43,6 +46,7 @@ enum dw_edma_map_format {
* @nr_irqs: total dma irq number
* @ops DMA channel to IRQ number mapping
* @flags - DW_EDMA_CHIP_LOCAL
+ * - DW_EDMA_CHIP_32BIT_DBI
* @reg_base DMA register base address
* @ll_wr_cnt DMA write link list number
* @ll_rd_cnt DMA read link list number
--
2.24.0.rc1