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From: Fenghua Yu <fenghua.yu@intel.com>
To: "Vinod Koul" <vkoul@kernel.org>, "Dave Jiang" <dave.jiang@intel.com>
Cc: dmaengine@vger.kernel.org,
	"linux-kernel" <linux-kernel@vger.kernel.org>,
	Fenghua Yu <fenghua.yu@intel.com>
Subject: [PATCH v2 3/3] dmaengine: idxd: Add descriptor definitions for translation fetch operation
Date: Fri,  3 Mar 2023 13:34:13 -0800	[thread overview]
Message-ID: <20230303213413.3357431-4-fenghua.yu@intel.com> (raw)
In-Reply-To: <20230303213413.3357431-1-fenghua.yu@intel.com>

The translation fetch operation (0x0A) fetches address translations for the
address range specified in the descriptor by issuing address translation
(ATS) requests to the IOMMU.

Add descriptor definitions for the operation so that user can use DSA
to accelerate translation fetch.

Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
---
 include/uapi/linux/idxd.h | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/include/uapi/linux/idxd.h b/include/uapi/linux/idxd.h
index 4c12e93a6aa6..fc47635b57dc 100644
--- a/include/uapi/linux/idxd.h
+++ b/include/uapi/linux/idxd.h
@@ -72,6 +72,7 @@ enum dsa_opcode {
 	DSA_OPCODE_CR_DELTA,
 	DSA_OPCODE_AP_DELTA,
 	DSA_OPCODE_DUALCAST,
+	DSA_OPCODE_TRANSL_FETCH,
 	DSA_OPCODE_CRCGEN = 0x10,
 	DSA_OPCODE_COPY_CRC,
 	DSA_OPCODE_DIF_CHECK,
@@ -182,6 +183,7 @@ struct dsa_hw_desc {
 		uint64_t	pattern;
 		uint64_t	desc_list_addr;
 		uint64_t	pattern_lower;
+		uint64_t	transl_fetch_addr;
 	};
 	union {
 		uint64_t	dst_addr;
@@ -192,6 +194,7 @@ struct dsa_hw_desc {
 	union {
 		uint32_t	xfer_size;
 		uint32_t	desc_count;
+		uint32_t	region_size;
 	};
 	uint16_t	int_handle;
 	uint16_t	rsvd1;
@@ -249,6 +252,12 @@ struct dsa_hw_desc {
 		/* Fill */
 		uint64_t	pattern_upper;
 
+		/* Translation fetch */
+		struct {
+			uint64_t	transl_fetch_res;
+			uint32_t	region_stride;
+		};
+
 		/* DIX generate */
 		struct {
 			uint8_t		dix_gen_res;
-- 
2.37.1


  parent reply	other threads:[~2023-03-03 21:34 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-03-03 21:34 [PATCH v2 0/3] Add descriptor definitions for a few new DSA operations Fenghua Yu
2023-03-03 21:34 ` [PATCH v2 1/3] dmaengine: idxd: Add descriptor definitions for 16 bytes of pattern in memory fill operation Fenghua Yu
2023-03-03 21:34 ` [PATCH v2 2/3] dmaengine: idxd: Add descriptor definitions for DIX generate operation Fenghua Yu
2023-03-03 21:34 ` Fenghua Yu [this message]
2023-03-29  2:05 ` [PATCH v2 0/3] Add descriptor definitions for a few new DSA operations Fenghua Yu
2023-03-31 11:55 ` Vinod Koul
2023-03-31 15:56   ` Fenghua Yu

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