From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9507DEB64D7 for ; Tue, 20 Jun 2023 13:35:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231495AbjFTNfy (ORCPT ); Tue, 20 Jun 2023 09:35:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36506 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232411AbjFTNfy (ORCPT ); Tue, 20 Jun 2023 09:35:54 -0400 Received: from relay4-d.mail.gandi.net (relay4-d.mail.gandi.net [IPv6:2001:4b98:dc4:8::224]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8BAB4B7; Tue, 20 Jun 2023 06:35:52 -0700 (PDT) X-GND-Sasl: kory.maincent@bootlin.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1687268150; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Uv+fbauLcYmaB3LHoaOohcS26YMyzwdt/TWV8wgjBuY=; b=lUwkRQ0+JfbrLLNfjnrE/nWP3Wg13DCjxCOejSe3er/wIWAlWKpnX8vqtt1L8wvEKZHs0k u8kwYJO+d6N2sGG0bAauaWlTH/5crEoCFVjRNxh7nJkdFv1fHRh1KHYPf9OxZD8VH1W2e5 pYkGEp1brBmzRYjoGTEldRb+uG4P0+dHdGogUbEYoZywOg7t1wolsKsiwtZRj4GUWRjdYC D1ZHq9yHysyz5WK5HNlw4tmZVXuLkEbgQ5N6Z3pKT7xQ86EpLQOGZp4bv2eQH6dahuvMfK ev9HGeogjFxVq9X/GsU4J6m7tbO1fvOvR926AfKqpBSC7c+q9r5DVi7eJr3ltA== X-GND-Sasl: kory.maincent@bootlin.com X-GND-Sasl: kory.maincent@bootlin.com X-GND-Sasl: kory.maincent@bootlin.com X-GND-Sasl: kory.maincent@bootlin.com X-GND-Sasl: kory.maincent@bootlin.com X-GND-Sasl: kory.maincent@bootlin.com X-GND-Sasl: kory.maincent@bootlin.com X-GND-Sasl: kory.maincent@bootlin.com Received: by mail.gandi.net (Postfix) with ESMTPSA id 0C58BE000A; Tue, 20 Jun 2023 13:35:49 +0000 (UTC) Date: Tue, 20 Jun 2023 15:35:49 +0200 From: =?UTF-8?Q?K=C3=B6ry?= Maincent To: Serge Semin Cc: Cai Huoqing , Manivannan Sadhasivam , Vinod Koul , Gustavo Pimentel , dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, Thomas Petazzoni , Herve Codina Subject: Re: [PATCH 5/9] dmaengine: dw-edma: HDMA: Fix possible race condition in remote setup Message-ID: <20230620153549.0677da97@kmaincent-XPS-13-7390> In-Reply-To: References: <20230609081654.330857-1-kory.maincent@bootlin.com> <20230609081654.330857-6-kory.maincent@bootlin.com> <20230619171550.3iyujmbre3dpe5oq@mobilestation.baikal.int> <20230619204105.620f87e6@kmaincent-XPS-13-7390> Organization: bootlin X-Mailer: Claws Mail 3.17.5 (GTK+ 2.24.32; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org On Tue, 20 Jun 2023 15:07:37 +0300 Serge Semin wrote: > > This one is only hypothetical. It appears to me that writing the control > > after the configuration of sar and dar is more relevant to prevent race > > issues and should be the usual coding choice. Also you are right saying > > that it will be relevant only for the LL tree entries recycling. > > Simple question from non DMA expert: isn't cyclic DMA mode recycle the LL > > tree entries? > > Ideally the driver should have been designed in the way you say: > define a ring of the Linked List entries and recycle the already used > entries while the already enabled entries are being handled by the > DMA-engine (a similar approach is described in the DW PCIe/eDMA hw > manual). DW eDMA engine CSRs and LLI descriptor provide enough > functionality for that. Alas the driver implementation is more > straightforward: > 1. Each DMA-engine config: SG-list, cyclic, interleaved is split up > into the "burst" entries. SG-list entries are directly mapped to the > eDMA "burst" entries. Cyclic iterations are unrolled into the > respective number of eDMA "burst" entries. A similar story with the > interleaved transactions. > 2. If there is no enough entries in the Linked-List memory to fully > execute the requested DMA-transfers, then another so called DW eDMA > "chunk" is allocated. > 3. DW eDMA engine executes the "chunks" one after another stopping at > the end of each one and recharging the engine with the next "chunk" until > the last one is finished. > > It isn't the most effective architecture, but that's how it was > originally developed by Gustavo. Anyway discussing it is a good food > for thoughts for the driver refactoring though.) thanks for enlightening me, then indeed we will never face the issue solved by this patches as we won't recycle LL tree entries.