From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9F0E9C001E0 for ; Sat, 21 Oct 2023 09:38:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229623AbjJUJiE (ORCPT ); Sat, 21 Oct 2023 05:38:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58294 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229472AbjJUJiE (ORCPT ); Sat, 21 Oct 2023 05:38:04 -0400 Received: from szxga03-in.huawei.com (szxga03-in.huawei.com [45.249.212.189]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 416121A4; Sat, 21 Oct 2023 02:37:59 -0700 (PDT) Received: from kwepemm000013.china.huawei.com (unknown [172.30.72.57]) by szxga03-in.huawei.com (SkyGuard) with ESMTP id 4SCGVJ32xtzMlpT; Sat, 21 Oct 2023 17:33:44 +0800 (CST) Received: from huawei.com (10.175.112.208) by kwepemm000013.china.huawei.com (7.193.23.81) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.31; Sat, 21 Oct 2023 17:37:52 +0800 From: Guo Mengqi To: , , , , , CC: , , Subject: [PATCH v5 2/2] dt-bindings: dma: HiSilicon: Add bindings for HiSilicon Ascend sdma Date: Sat, 21 Oct 2023 17:34:53 +0800 Message-ID: <20231021093454.39822-3-guomengqi3@huawei.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231021093454.39822-1-guomengqi3@huawei.com> References: <20231021093454.39822-1-guomengqi3@huawei.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.175.112.208] X-ClientProxiedBy: dggems704-chm.china.huawei.com (10.3.19.181) To kwepemm000013.china.huawei.com (7.193.23.81) X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org Add device-tree binding documentation for sdma hardware on HiSilicon Ascend SoC families. Signed-off-by: Guo Mengqi --- .../bindings/dma/hisilicon,ascend-sdma.yaml | 73 +++++++++++++++++++ 1 file changed, 73 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/hisilicon,ascend-sdma.yaml diff --git a/Documentation/devicetree/bindings/dma/hisilicon,ascend-sdma.yaml b/Documentation/devicetree/bindings/dma/hisilicon,ascend-sdma.yaml new file mode 100644 index 000000000000..7b452b54fe0c --- /dev/null +++ b/Documentation/devicetree/bindings/dma/hisilicon,ascend-sdma.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/hisilicon,ascend-sdma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: HiSilicon Ascend System DMA (SDMA) controller + +description: | + The Ascend SDMA controller is used for transferring data + in system memory. + +maintainers: + - Guo Mengqi + +allOf: + - $ref: dma-controller.yaml# + +properties: + compatible: + enum: + - hisilicon,ascend310-sdma + - hisilicon,ascend910-sdma + + reg: + maxItems: 1 + + '#dma-cells': + const: 1 + description: + Clients specify a single cell with channel number. + + dma-channel-mask: + minItems: 1 + maxItems: 2 + + iommus: + maxItems: 1 + + pasid-num-bits: + description: | + This tells smmu that this device supports iommu-sva feature. + This determines the maximum number of digits in the pasid. + maximum: 0x10 + + dma-coherent: true + + dma-can-stall: true + +required: + - compatible + - reg + - dma-channel-mask + - '#dma-cells' + - iommus + - pasid-num-bits + +additionalProperties: false + +examples: + - | + dma-controller@880e0000 { + compatible = "hisilicon,ascend310-sdma"; + reg = <0x880e0000 0x10000>; + dma-channel-mask = <0xff00>; + iommus = <&smmu 0x7f46>; + pasid-num-bits = <0x10>; + dma-coherent; + dma-can-stall; + #dma-cells = <1>; + }; + +... -- 2.17.1