* [PATCH RESEND 1/2] dmaengine: dw-edma: Move "Set consumer cycle" into first condition in dw_hdma_v0_core_start() [not found] <cover.1720176660.git.zheng.dongxiong@outlook.com> @ 2024-07-05 10:57 ` zheng.dongxiong 2024-07-05 14:12 ` Manivannan Sadhasivam 2024-07-05 10:57 ` [PATCH RESEND 2/2] damengine: dw-edma: Add msi wartermark configuration zheng.dongxiong 1 sibling, 1 reply; 7+ messages in thread From: zheng.dongxiong @ 2024-07-05 10:57 UTC (permalink / raw) To: manivannan.sadhasivam, fancer.lancer, vkoul Cc: dmaengine, linux-kernel, zheng.dongxiong Two or more chunks are used in a transfer, Consumer cycle only needs to be set on the first transfer. Signed-off-by: zheng.dongxiong <zheng.dongxiong@outlook.com> --- drivers/dma/dw-edma/dw-hdma-v0-core.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/dma/dw-edma/dw-hdma-v0-core.c b/drivers/dma/dw-edma/dw-hdma-v0-core.c index 10e8f0715..d77051d1e 100644 --- a/drivers/dma/dw-edma/dw-hdma-v0-core.c +++ b/drivers/dma/dw-edma/dw-hdma-v0-core.c @@ -262,10 +262,10 @@ static void dw_hdma_v0_core_start(struct dw_edma_chunk *chunk, bool first) lower_32_bits(chunk->ll_region.paddr)); SET_CH_32(dw, chan->dir, chan->id, llp.msb, upper_32_bits(chunk->ll_region.paddr)); + /* Set consumer cycle */ + SET_CH_32(dw, chan->dir, chan->id, cycle_sync, + HDMA_V0_CONSUMER_CYCLE_STAT | HDMA_V0_CONSUMER_CYCLE_BIT); } - /* Set consumer cycle */ - SET_CH_32(dw, chan->dir, chan->id, cycle_sync, - HDMA_V0_CONSUMER_CYCLE_STAT | HDMA_V0_CONSUMER_CYCLE_BIT); dw_hdma_v0_sync_ll_data(chunk); -- 2.34.1 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH RESEND 1/2] dmaengine: dw-edma: Move "Set consumer cycle" into first condition in dw_hdma_v0_core_start() 2024-07-05 10:57 ` [PATCH RESEND 1/2] dmaengine: dw-edma: Move "Set consumer cycle" into first condition in dw_hdma_v0_core_start() zheng.dongxiong @ 2024-07-05 14:12 ` Manivannan Sadhasivam 2024-07-06 8:40 ` dongxiong zheng 0 siblings, 1 reply; 7+ messages in thread From: Manivannan Sadhasivam @ 2024-07-05 14:12 UTC (permalink / raw) To: zheng.dongxiong; +Cc: fancer.lancer, vkoul, dmaengine, linux-kernel On Fri, Jul 05, 2024 at 06:57:34PM +0800, zheng.dongxiong wrote: > Two or more chunks are used in a transfer, > Consumer cycle only needs to be set on the first transfer. > Can you please reference the section of the spec that mentions this behavior? - Mani > Signed-off-by: zheng.dongxiong <zheng.dongxiong@outlook.com> > --- > drivers/dma/dw-edma/dw-hdma-v0-core.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/dma/dw-edma/dw-hdma-v0-core.c b/drivers/dma/dw-edma/dw-hdma-v0-core.c > index 10e8f0715..d77051d1e 100644 > --- a/drivers/dma/dw-edma/dw-hdma-v0-core.c > +++ b/drivers/dma/dw-edma/dw-hdma-v0-core.c > @@ -262,10 +262,10 @@ static void dw_hdma_v0_core_start(struct dw_edma_chunk *chunk, bool first) > lower_32_bits(chunk->ll_region.paddr)); > SET_CH_32(dw, chan->dir, chan->id, llp.msb, > upper_32_bits(chunk->ll_region.paddr)); > + /* Set consumer cycle */ > + SET_CH_32(dw, chan->dir, chan->id, cycle_sync, > + HDMA_V0_CONSUMER_CYCLE_STAT | HDMA_V0_CONSUMER_CYCLE_BIT); > } > - /* Set consumer cycle */ > - SET_CH_32(dw, chan->dir, chan->id, cycle_sync, > - HDMA_V0_CONSUMER_CYCLE_STAT | HDMA_V0_CONSUMER_CYCLE_BIT); > > dw_hdma_v0_sync_ll_data(chunk); > > -- > 2.34.1 > -- மணிவண்ணன் சதாசிவம் ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH RESEND 1/2] dmaengine: dw-edma: Move "Set consumer cycle" into first condition in dw_hdma_v0_core_start() 2024-07-05 14:12 ` Manivannan Sadhasivam @ 2024-07-06 8:40 ` dongxiong zheng 2024-07-21 8:57 ` Manivannan Sadhasivam 0 siblings, 1 reply; 7+ messages in thread From: dongxiong zheng @ 2024-07-06 8:40 UTC (permalink / raw) To: manivannan.sadhasivam Cc: dmaengine, fancer.lancer, linux-kernel, vkoul, zhengdongxiong Hi, Manivannan Sadhasivam: Thank you for your reply! On Fri, Jul 05, 2024 at 19:42:41 +0530, Manivannan Sadhasivam wrote: > On Fri, Jul 05, 2024 at 06:57:34PM +0800, zheng.dongxiong wrote: > > Two or more chunks are used in a transfer, > > Consumer cycle only needs to be set on the first transfer. > > > > Can you please reference the section of the spec that mentions this behavior? > > - Mani > Reference: Chapter 6.4.9.1 LL Operation Overview: "Figure 6-23 Linked List Flow for Producer and Consumer" in DesignWare Cores PCI Express Controller Databook (Version 6.00a June 2022) The CCS must be set when L1 is executed for the first time, After an interruption is triggered, CCS does not need to be configured again when L3 is executed. > > Signed-off-by: zheng.dongxiong <zheng.dongxiong@outlook.com> > > --- > > drivers/dma/dw-edma/dw-hdma-v0-core.c | 6 +++--- > > 1 file changed, 3 insertions(+), 3 deletions(-) > > > > diff --git a/drivers/dma/dw-edma/dw-hdma-v0-core.c b/drivers/dma/dw-edma/dw-hdma-v0-core.c > > index 10e8f0715..d77051d1e 100644 > > --- a/drivers/dma/dw-edma/dw-hdma-v0-core.c > > +++ b/drivers/dma/dw-edma/dw-hdma-v0-core.c > > @@ -262,10 +262,10 @@ static void dw_hdma_v0_core_start(struct dw_edma_chunk *chunk, bool first) > > lower_32_bits(chunk->ll_region.paddr)); > > SET_CH_32(dw, chan->dir, chan->id, llp.msb, > > upper_32_bits(chunk->ll_region.paddr)); > > + /* Set consumer cycle */ > > + SET_CH_32(dw, chan->dir, chan->id, cycle_sync, > > + HDMA_V0_CONSUMER_CYCLE_STAT | HDMA_V0_CONSUMER_CYCLE_BIT); > > } > > - /* Set consumer cycle */ > > - SET_CH_32(dw, chan->dir, chan->id, cycle_sync, > > - HDMA_V0_CONSUMER_CYCLE_STAT | HDMA_V0_CONSUMER_CYCLE_BIT); > > > > dw_hdma_v0_sync_ll_data(chunk); > > > > -- > > 2.34.1 > > > Test brief: hdma set chan->ll_max == 1, then user alloc two or more scatterlist, start transfer. -- Regards, dongxiong zheng ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH RESEND 1/2] dmaengine: dw-edma: Move "Set consumer cycle" into first condition in dw_hdma_v0_core_start() 2024-07-06 8:40 ` dongxiong zheng @ 2024-07-21 8:57 ` Manivannan Sadhasivam 0 siblings, 0 replies; 7+ messages in thread From: Manivannan Sadhasivam @ 2024-07-21 8:57 UTC (permalink / raw) To: dongxiong zheng; +Cc: dmaengine, fancer.lancer, linux-kernel, vkoul On Sat, Jul 06, 2024 at 04:40:10PM +0800, dongxiong zheng wrote: > Hi, Manivannan Sadhasivam: > Thank you for your reply! > > On Fri, Jul 05, 2024 at 19:42:41 +0530, Manivannan Sadhasivam wrote: > > On Fri, Jul 05, 2024 at 06:57:34PM +0800, zheng.dongxiong wrote: > > > Two or more chunks are used in a transfer, > > > Consumer cycle only needs to be set on the first transfer. > > > > > > > Can you please reference the section of the spec that mentions this behavior? > > > > - Mani > > > > Reference: > Chapter 6.4.9.1 LL Operation Overview: > "Figure 6-23 Linked List Flow for Producer and Consumer" in > DesignWare Cores PCI Express Controller Databook (Version 6.00a June 2022) > > The CCS must be set when L1 is executed for the first time, After an interruption is > triggered, CCS does not need to be configured again when L3 is executed. > Okay, please include this reference in commit message and send v2. - Mani > > > Signed-off-by: zheng.dongxiong <zheng.dongxiong@outlook.com> > > > --- > > > drivers/dma/dw-edma/dw-hdma-v0-core.c | 6 +++--- > > > 1 file changed, 3 insertions(+), 3 deletions(-) > > > > > > diff --git a/drivers/dma/dw-edma/dw-hdma-v0-core.c b/drivers/dma/dw-edma/dw-hdma-v0-core.c > > > index 10e8f0715..d77051d1e 100644 > > > --- a/drivers/dma/dw-edma/dw-hdma-v0-core.c > > > +++ b/drivers/dma/dw-edma/dw-hdma-v0-core.c > > > @@ -262,10 +262,10 @@ static void dw_hdma_v0_core_start(struct dw_edma_chunk *chunk, bool first) > > > lower_32_bits(chunk->ll_region.paddr)); > > > SET_CH_32(dw, chan->dir, chan->id, llp.msb, > > > upper_32_bits(chunk->ll_region.paddr)); > > > + /* Set consumer cycle */ > > > + SET_CH_32(dw, chan->dir, chan->id, cycle_sync, > > > + HDMA_V0_CONSUMER_CYCLE_STAT | HDMA_V0_CONSUMER_CYCLE_BIT); > > > } > > > - /* Set consumer cycle */ > > > - SET_CH_32(dw, chan->dir, chan->id, cycle_sync, > > > - HDMA_V0_CONSUMER_CYCLE_STAT | HDMA_V0_CONSUMER_CYCLE_BIT); > > > > > > dw_hdma_v0_sync_ll_data(chunk); > > > > > > -- > > > 2.34.1 > > > > > > > Test brief: hdma set chan->ll_max == 1, > then user alloc two or more scatterlist, start transfer. > > -- > Regards, > dongxiong zheng > -- மணிவண்ணன் சதாசிவம் ^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH RESEND 2/2] damengine: dw-edma: Add msi wartermark configuration [not found] <cover.1720176660.git.zheng.dongxiong@outlook.com> 2024-07-05 10:57 ` [PATCH RESEND 1/2] dmaengine: dw-edma: Move "Set consumer cycle" into first condition in dw_hdma_v0_core_start() zheng.dongxiong @ 2024-07-05 10:57 ` zheng.dongxiong 2024-07-05 14:11 ` Manivannan Sadhasivam 1 sibling, 1 reply; 7+ messages in thread From: zheng.dongxiong @ 2024-07-05 10:57 UTC (permalink / raw) To: manivannan.sadhasivam, fancer.lancer, vkoul Cc: dmaengine, linux-kernel, zheng.dongxiong HDMA trigger wartermark interrupt, When use the RIE flag. PCIe RC will trigger AER, If msi wartermark addr is not configuration. This patch fix it by add msi wartermark configuration Signed-off-by: zheng.dongxiong <zheng.dongxiong@outlook.com> --- drivers/dma/dw-edma/dw-hdma-v0-core.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/dma/dw-edma/dw-hdma-v0-core.c b/drivers/dma/dw-edma/dw-hdma-v0-core.c index d77051d1e..c4d15a7a7 100644 --- a/drivers/dma/dw-edma/dw-hdma-v0-core.c +++ b/drivers/dma/dw-edma/dw-hdma-v0-core.c @@ -280,6 +280,9 @@ static void dw_hdma_v0_core_ch_config(struct dw_edma_chan *chan) /* MSI done addr - low, high */ SET_CH_32(dw, chan->dir, chan->id, msi_stop.lsb, chan->msi.address_lo); SET_CH_32(dw, chan->dir, chan->id, msi_stop.msb, chan->msi.address_hi); + /* MSI watermark addr - low, high */ + SET_CH_32(dw, chan->dir, chan->id, msi_watermark.lsb, chan->msi.address_lo); + SET_CH_32(dw, chan->dir, chan->id, msi_watermark.msb, chan->msi.address_hi); /* MSI abort addr - low, high */ SET_CH_32(dw, chan->dir, chan->id, msi_abort.lsb, chan->msi.address_lo); SET_CH_32(dw, chan->dir, chan->id, msi_abort.msb, chan->msi.address_hi); -- 2.34.1 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH RESEND 2/2] damengine: dw-edma: Add msi wartermark configuration 2024-07-05 10:57 ` [PATCH RESEND 2/2] damengine: dw-edma: Add msi wartermark configuration zheng.dongxiong @ 2024-07-05 14:11 ` Manivannan Sadhasivam 2024-07-06 7:59 ` dongxiong zheng 0 siblings, 1 reply; 7+ messages in thread From: Manivannan Sadhasivam @ 2024-07-05 14:11 UTC (permalink / raw) To: zheng.dongxiong; +Cc: fancer.lancer, vkoul, dmaengine, linux-kernel On Fri, Jul 05, 2024 at 06:57:35PM +0800, zheng.dongxiong wrote: > HDMA trigger wartermark interrupt, When use the RIE flag. > PCIe RC will trigger AER, If msi wartermark addr is not configuration. > This patch fix it by add msi wartermark configuration > > Signed-off-by: zheng.dongxiong <zheng.dongxiong@outlook.com> HDMA driver is not at all using watermark interrupts. So we should be disabling them altogether. See: https://lore.kernel.org/dmaengine/1720187733-5380-3-git-send-email-quic_msarkar@quicinc.com/ - Mani > --- > drivers/dma/dw-edma/dw-hdma-v0-core.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/dma/dw-edma/dw-hdma-v0-core.c b/drivers/dma/dw-edma/dw-hdma-v0-core.c > index d77051d1e..c4d15a7a7 100644 > --- a/drivers/dma/dw-edma/dw-hdma-v0-core.c > +++ b/drivers/dma/dw-edma/dw-hdma-v0-core.c > @@ -280,6 +280,9 @@ static void dw_hdma_v0_core_ch_config(struct dw_edma_chan *chan) > /* MSI done addr - low, high */ > SET_CH_32(dw, chan->dir, chan->id, msi_stop.lsb, chan->msi.address_lo); > SET_CH_32(dw, chan->dir, chan->id, msi_stop.msb, chan->msi.address_hi); > + /* MSI watermark addr - low, high */ > + SET_CH_32(dw, chan->dir, chan->id, msi_watermark.lsb, chan->msi.address_lo); > + SET_CH_32(dw, chan->dir, chan->id, msi_watermark.msb, chan->msi.address_hi); > /* MSI abort addr - low, high */ > SET_CH_32(dw, chan->dir, chan->id, msi_abort.lsb, chan->msi.address_lo); > SET_CH_32(dw, chan->dir, chan->id, msi_abort.msb, chan->msi.address_hi); > -- > 2.34.1 > -- மணிவண்ணன் சதாசிவம் ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH RESEND 2/2] damengine: dw-edma: Add msi wartermark configuration 2024-07-05 14:11 ` Manivannan Sadhasivam @ 2024-07-06 7:59 ` dongxiong zheng 0 siblings, 0 replies; 7+ messages in thread From: dongxiong zheng @ 2024-07-06 7:59 UTC (permalink / raw) To: manivannan.sadhasivam Cc: dmaengine, fancer.lancer, linux-kernel, vkoul, zhengdongxiong > On Fri, Jul 05, 2024 at 06:57:35PM +0800, zheng.dongxiong wrote: > > HDMA trigger wartermark interrupt, When use the RIE flag. > > PCIe RC will trigger AER, If msi wartermark addr is not configuration. > > This patch fix it by add msi wartermark configuration > > > > Signed-off-by: zheng.dongxiong <zheng.dongxiong@outlook.com> > > HDMA driver is not at all using watermark interrupts. So we should be disabling > them altogether. > > See: https://lore.kernel.org/dmaengine/1720187733-5380-3-git-send-email-quic_msarkar@quicinc.com/ > > - Mani > Hi Mani: Ok, Thanks you! > > --- > > drivers/dma/dw-edma/dw-hdma-v0-core.c | 3 +++ > > 1 file changed, 3 insertions(+) > > > > diff --git a/drivers/dma/dw-edma/dw-hdma-v0-core.c b/drivers/dma/dw-edma/dw-hdma-v0-core.c > > index d77051d1e..c4d15a7a7 100644 > > --- a/drivers/dma/dw-edma/dw-hdma-v0-core.c > > +++ b/drivers/dma/dw-edma/dw-hdma-v0-core.c > > @@ -280,6 +280,9 @@ static void dw_hdma_v0_core_ch_config(struct dw_edma_chan *chan) > > /* MSI done addr - low, high */ > > SET_CH_32(dw, chan->dir, chan->id, msi_stop.lsb, chan->msi.address_lo); > > SET_CH_32(dw, chan->dir, chan->id, msi_stop.msb, chan->msi.address_hi); > > + /* MSI watermark addr - low, high */ > > + SET_CH_32(dw, chan->dir, chan->id, msi_watermark.lsb, chan->msi.address_lo); > > + SET_CH_32(dw, chan->dir, chan->id, msi_watermark.msb, chan->msi.address_hi); > > /* MSI abort addr - low, high */ > > SET_CH_32(dw, chan->dir, chan->id, msi_abort.lsb, chan->msi.address_lo); > > SET_CH_32(dw, chan->dir, chan->id, msi_abort.msb, chan->msi.address_hi); > > -- > > 2.34.1 > > > Regards, dongxiong zheng ^ permalink raw reply [flat|nested] 7+ messages in thread
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[not found] <cover.1720176660.git.zheng.dongxiong@outlook.com>
2024-07-05 10:57 ` [PATCH RESEND 1/2] dmaengine: dw-edma: Move "Set consumer cycle" into first condition in dw_hdma_v0_core_start() zheng.dongxiong
2024-07-05 14:12 ` Manivannan Sadhasivam
2024-07-06 8:40 ` dongxiong zheng
2024-07-21 8:57 ` Manivannan Sadhasivam
2024-07-05 10:57 ` [PATCH RESEND 2/2] damengine: dw-edma: Add msi wartermark configuration zheng.dongxiong
2024-07-05 14:11 ` Manivannan Sadhasivam
2024-07-06 7:59 ` dongxiong zheng
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