From: Conor Dooley <conor@kernel.org>
To: Larisa Grigore <larisa.grigore@oss.nxp.com>
Cc: Frank Li <Frank.Li@nxp.com>, Vinod Koul <vkoul@kernel.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>, Peng Fan <peng.fan@nxp.com>,
imx@lists.linux.dev, dmaengine@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
s32@nxp.com, Christophe Lizzi <clizzi@redhat.com>,
Alberto Ruiz <aruizrui@redhat.com>,
Enric Balletbo <eballetb@redhat.com>
Subject: Re: [PATCH v3 3/5] dt-bindings: dma: fsl-edma: add nxp,s32g2-edma compatible string
Date: Thu, 19 Dec 2024 19:46:21 +0000 [thread overview]
Message-ID: <20241219-flirt-gab-dbacc809cca4@spud> (raw)
In-Reply-To: <20241219102415.1208328-4-larisa.grigore@oss.nxp.com>
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On Thu, Dec 19, 2024 at 12:24:12PM +0200, Larisa Grigore wrote:
> Introduce the compatible strings 'nxp,s32g2-edma' and 'nxp,s32g3-edma' to
> enable the support for the eDMAv3 present on S32G2/S32G3 platforms.
>
> The S32G2/S32G3 eDMA architecture features 32 DMA channels. Each of the
> two eDMA instances is integrated with two DMAMUX blocks.
>
> Another particularity of these SoCs is that the interrupts are shared
> between channels in the following way:
> - DMA Channels 0-15 share the 'tx-0-15' interrupt
> - DMA Channels 16-31 share the 'tx-16-31' interrupt
> - all channels share the 'err' interrupt
>
> Signed-off-by: Larisa Grigore <larisa.grigore@oss.nxp.com>
> Reviewed-by: Frank Li <Frank.Li@nxp.com>
> ---
> .../devicetree/bindings/dma/fsl,edma.yaml | 34 +++++++++++++++++++
> 1 file changed, 34 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/dma/fsl,edma.yaml b/Documentation/devicetree/bindings/dma/fsl,edma.yaml
> index d54140f18d34..4f925469533e 100644
> --- a/Documentation/devicetree/bindings/dma/fsl,edma.yaml
> +++ b/Documentation/devicetree/bindings/dma/fsl,edma.yaml
> @@ -26,9 +26,13 @@ properties:
> - fsl,imx93-edma3
> - fsl,imx93-edma4
> - fsl,imx95-edma5
> + - nxp,s32g2-edma
> - items:
> - const: fsl,ls1028a-edma
> - const: fsl,vf610-edma
> + - items:
> + - const: nxp,s32g3-edma
> + - const: nxp,s32g2-edma
>
> reg:
> minItems: 1
> @@ -221,6 +225,36 @@ allOf:
> properties:
> power-domains: false
>
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: nxp,s32g2-edma
Your property ordering below is a bit odd, but it matches what exists
currently so
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Cheers,
Conor.
> + then:
> + properties:
> + clocks:
> + minItems: 2
> + maxItems: 2
> + clock-names:
> + items:
> + - const: dmamux0
> + - const: dmamux1
> + interrupts:
> + minItems: 3
> + maxItems: 3
> + interrupt-names:
> + items:
> + - const: tx-0-15
> + - const: tx-16-31
> + - const: err
> + reg:
> + minItems: 3
> + maxItems: 3
> + "#dma-cells":
> + const: 2
> + dma-channels:
> + const: 32
> +
> unevaluatedProperties: false
>
> examples:
> --
> 2.47.0
>
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next prev parent reply other threads:[~2024-12-19 19:46 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-12-19 10:24 [PATCH v3 0/5] Add eDMAv3 support for S32G2/S32G3 SoCs Larisa Grigore
2024-12-19 10:24 ` [PATCH v3 1/5] dmaengine: fsl-edma: select of_dma_xlate based on the dmamuxs presence Larisa Grigore
2024-12-19 10:24 ` [PATCH v3 2/5] dmaengine: fsl-edma: remove FSL_EDMA_DRV_SPLIT_REG check when parsing muxbase Larisa Grigore
2024-12-19 10:24 ` [PATCH v3 3/5] dt-bindings: dma: fsl-edma: add nxp,s32g2-edma compatible string Larisa Grigore
2024-12-19 19:46 ` Conor Dooley [this message]
2024-12-19 10:24 ` [PATCH v3 4/5] dmaengine: fsl-edma: add support for S32G based platforms Larisa Grigore
2024-12-19 10:24 ` [PATCH v3 5/5] dmaengine: fsl-edma: read/write multiple registers in cyclic transactions Larisa Grigore
2024-12-24 10:42 ` [PATCH v3 0/5] Add eDMAv3 support for S32G2/S32G3 SoCs Vinod Koul
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