From: Devendra K Verma <devendra.verma@amd.com>
To: <bhelgaas@google.com>, <mani@kernel.org>, <vkoul@kernel.org>
Cc: <dmaengine@vger.kernel.org>, <linux-pci@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <michal.simek@amd.com>
Subject: [PATCH v3 0/2] Add AMD MDB Endpoint and non-LL mode Support
Date: Tue, 16 Sep 2025 17:24:09 +0530 [thread overview]
Message-ID: <20250916115411.23655-1-devendra.verma@amd.com> (raw)
This series of patch support the following:
- AMD MDB Endpoint Support, as part of this patch following are
added:
o AMD supported device ID and vendor ID (Xilinx)
o AMD MDB specific driver data
o AMD specific VSEC capabilities to retrieve the base of
phys address of MDB side DDR
o Logic to assign the offsets to LL and data blocks if
more number of channels are enabled than configured
in the given pci_data struct.
- Addition of non-LL mode
o The IP supported non-LL mode functions
o Flexibility to choose non-LL mode via dma_slave_config
param peripheral_config, by the client
o Allow IP utilization if LL mode is not available
Devendra K Verma (2):
dmaengine: dw-edma: Add AMD MDB Endpoint Support
dmaengine: dw-edma: Add non-LL mode
drivers/dma/dw-edma/dw-edma-core.c | 38 +++++++-
drivers/dma/dw-edma/dw-edma-core.h | 1 +
drivers/dma/dw-edma/dw-edma-pcie.c | 178 ++++++++++++++++++++++++++++++++--
drivers/dma/dw-edma/dw-hdma-v0-core.c | 62 +++++++++++-
include/linux/dma/edma.h | 1 +
5 files changed, 266 insertions(+), 14 deletions(-)
--
1.8.3.1
next reply other threads:[~2025-09-16 11:54 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-16 11:54 Devendra K Verma [this message]
2025-09-16 11:54 ` [PATCH v3 1/2] dmaengine: dw-edma: Add AMD MDB Endpoint Support Devendra K Verma
2025-09-16 11:54 ` [PATCH v3 2/2] dmaengine: dw-edma: Add non-LL mode Devendra K Verma
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