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From: Jean-Michel Hautbois via B4 Relay <devnull+jeanmichel.hautbois.yoseli.org@kernel.org>
To: Frank Li <Frank.Li@nxp.com>, Vinod Koul <vkoul@kernel.org>,
	 Angelo Dureghello <angelo@sysam.it>
Cc: Greg Ungerer <gerg@linux-m68k.org>,
	imx@lists.linux.dev,  dmaengine@vger.kernel.org,
	linux-m68k@lists.linux-m68k.org,  linux-kernel@vger.kernel.org,
	 Jean-Michel Hautbois <jeanmichel.hautbois@yoseli.org>
Subject: [PATCH v2 1/5] dma: fsl-edma: Add FSL_EDMA_DRV_MCF flag for ColdFire eDMA
Date: Wed, 26 Nov 2025 09:36:02 +0100	[thread overview]
Message-ID: <20251126-dma-coldfire-v2-1-5b1e4544d609@yoseli.org> (raw)
In-Reply-To: <20251126-dma-coldfire-v2-0-5b1e4544d609@yoseli.org>

From: Jean-Michel Hautbois <jeanmichel.hautbois@yoseli.org>

Add FSL_EDMA_DRV_MCF driver flag to identify MCF ColdFire eDMA
controllers which have a native M68K register layout.

The edma_writeb() function applies an XOR ^ 0x3 byte-lane adjustment for
big-endian eDMA controllers where byte registers within a 32-bit word
need address correction.

However, the MCF54418 eDMA 8-bit registers (SERQ, CERQ, SEEI, CEEI,
CINT, CERR, SSRT, CDNE) are located at sequential byte addresses
(0x4018-0x401F) as documented in the MCF54418 Reference Manual Table
19-2. No byte-lane adjustment is needed, as applying the XOR causes
writes to target incorrect registers (writing to CERR at 0x401D would
actually access SSRT at 0x401E).

Set this flag in the MCF eDMA driver to bypass the XOR adjustment and
access registers at their documented addresses.

Reviewed-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Jean-Michel Hautbois <jeanmichel.hautbois@yoseli.org>
---
 drivers/dma/fsl-edma-common.h | 5 ++++-
 drivers/dma/mcf-edma-main.c   | 2 +-
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/dma/fsl-edma-common.h b/drivers/dma/fsl-edma-common.h
index 205a96489094..4c86f2f39c1d 100644
--- a/drivers/dma/fsl-edma-common.h
+++ b/drivers/dma/fsl-edma-common.h
@@ -225,6 +225,8 @@ struct fsl_edma_desc {
 #define FSL_EDMA_DRV_TCD64		BIT(15)
 /* All channel ERR IRQ share one IRQ line */
 #define FSL_EDMA_DRV_ERRIRQ_SHARE       BIT(16)
+/* MCF eDMA: Different register layout, no XOR for byte access */
+#define FSL_EDMA_DRV_MCF                BIT(17)
 
 
 #define FSL_EDMA_DRV_EDMA3	(FSL_EDMA_DRV_SPLIT_REG |	\
@@ -419,7 +421,8 @@ static inline void edma_writeb(struct fsl_edma_engine *edma,
 			       u8 val, void __iomem *addr)
 {
 	/* swap the reg offset for these in big-endian mode */
-	if (edma->big_endian)
+	/* MCF eDMA has different register layout, no XOR needed */
+	if (edma->big_endian && !(edma->drvdata->flags & FSL_EDMA_DRV_MCF))
 		iowrite8(val, (void __iomem *)((unsigned long)addr ^ 0x3));
 	else
 		iowrite8(val, addr);
diff --git a/drivers/dma/mcf-edma-main.c b/drivers/dma/mcf-edma-main.c
index 9e1c6400c77b..f95114829d80 100644
--- a/drivers/dma/mcf-edma-main.c
+++ b/drivers/dma/mcf-edma-main.c
@@ -145,7 +145,7 @@ static void mcf_edma_irq_free(struct platform_device *pdev,
 }
 
 static struct fsl_edma_drvdata mcf_data = {
-	.flags = FSL_EDMA_DRV_EDMA64,
+	.flags = FSL_EDMA_DRV_EDMA64 | FSL_EDMA_DRV_MCF,
 	.setup_irq = mcf_edma_irq_init,
 };
 

-- 
2.39.5



  reply	other threads:[~2025-11-26  8:36 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-11-26  8:36 [PATCH v2 0/5] dma: fsl/mcf-edma: Bug fixes and enhancements for ColdFire support Jean-Michel Hautbois via B4 Relay
2025-11-26  8:36 ` Jean-Michel Hautbois via B4 Relay [this message]
2025-11-26  8:36 ` [PATCH v2 2/5] dma: mcf-edma: Add per-channel IRQ naming for debugging Jean-Michel Hautbois via B4 Relay
2025-11-26 16:12   ` Frank Li
2025-12-16 15:26     ` Vinod Koul
2025-12-16 15:38       ` Frank Li
2025-12-17  6:34         ` Jean-Michel Hautbois
2025-12-17 16:21           ` Frank Li
2025-11-26  8:36 ` [PATCH v2 3/5] dma: mcf-edma: Fix interrupt handler for 64 DMA channels Jean-Michel Hautbois via B4 Relay
2025-11-26  8:36 ` [PATCH v2 4/5] dma: fsl-edma: Move error handler out of header file Jean-Michel Hautbois via B4 Relay
2025-11-26  8:36 ` [PATCH v2 5/5] dma: mcf-edma: Fix error handler for all 64 DMA channels Jean-Michel Hautbois via B4 Relay
2025-11-26 16:14   ` Frank Li
2025-12-16 15:27 ` [PATCH v2 0/5] dma: fsl/mcf-edma: Bug fixes and enhancements for ColdFire support Vinod Koul

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