From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 84D794A13A2; Mon, 11 May 2026 19:16:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778526997; cv=none; b=GHFqSweSXoOByipiakPKroWpJaRWdLj6wwa4gOTo/fFIPlQv7KRSHNN879YA3SSQA9WmjUCb5F1Kc+17po7IF9F9Gnx2VpHA7wY0w9C8fEQEnWqZLUDYVS3fBgNehzw6wT+/AM5FyUBXjdolLCMR54Kuz8FXW0EaCM8wS7oPLBk= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778526997; c=relaxed/simple; bh=p6RJfuGgVOjbO2AC07tSsL0VZfxUHgZN+0PancIMbDc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Ilajs4YTo3Vl1WSwMQrBOu+Zsa3bLVqyYBAt6bb/aemv/mQRqciRW5y8uyj0LtaE97o+UyWsgtMDfZjBt4YJTCwd4XzrVfTMj20VK0/OZRFjjbIZ7Mt2tHR949YXrsnbeKQdDbUjqsmEKc4qhyLotG2hRn8iVxGSbsOLbzQ2PZw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=LKJS/g7U; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="LKJS/g7U" Received: by smtp.kernel.org (Postfix) with ESMTPS id 55A45C2BCFC; Mon, 11 May 2026 19:16:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1778526997; bh=p6RJfuGgVOjbO2AC07tSsL0VZfxUHgZN+0PancIMbDc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=LKJS/g7UDdLl3gRKvqS+STZmWWL7yrAl4k0uvtI6Dz6sd74CYaS1WB3fSD+39DJpA nmNC4nGfOIvCkW/KFKDgYr5I2ENn2MP+ZgjehFUlp14bDOv3YcvV+BBG0IwOEOKqOm 7hPo8XeuGu5g+NpssEnRKBZLsaLsGhA+a1HvKHVn/3EwuQvVFdwjmCBzqJyV3cB/C/ BcOozrk6uAzXSogXWjZ1/guLrixP8FwaObA65VVf6ZEJlFGVM95L1mPdKda/foJ4jT UDlbwBrPhEjBXOcmEl446voZIoGyVrp51NjGt5r6XrGl1hMSvYIyOZ0pKCRDid043/ 4MVzHJ6MJcknA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4E330CD37BE; Mon, 11 May 2026 19:16:37 +0000 (UTC) From: Nathan Lynch via B4 Relay Date: Mon, 11 May 2026 14:16:15 -0500 Subject: [PATCH v2 03/23] dmaengine: sdxi: Add PCI initialization Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260511-sdxi-base-v2-3-889cfed17e3f@amd.com> References: <20260511-sdxi-base-v2-0-889cfed17e3f@amd.com> In-Reply-To: <20260511-sdxi-base-v2-0-889cfed17e3f@amd.com> To: Vinod Koul , Frank Li Cc: Bjorn Helgaas , David Rientjes , John.Kariuki@amd.com, Kinsey Ho , Mario Limonciello , PradeepVineshReddy.Kodamati@amd.com, Shivank Garg , Stephen Bates , Wei Huang , Wei Xu , dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, Jonathan Cameron , Nathan Lynch X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1778526994; l=6987; i=nathan.lynch@amd.com; s=20260410; h=from:subject:message-id; bh=Jr/4QKf8JJOoYOpO1PMCwsIuwzKb0eqSFB9z91gGX0w=; b=iS7K0F3kxuiokKzkHZ+v2FPj9hh3Kvd4IKMybGZRuBR7yakUe4g98s8dXGUlMj4dpqEdlMXsQ +fpM3v3KHchDJnWnKatmiz/0n5Qce0OkyB/pns0ViBT/6/VaYxdLlVN X-Developer-Key: i=nathan.lynch@amd.com; a=ed25519; pk=PK4ozhq+/z9/2Jl5rgDmvHa9raVomv79qM8p1RAFpEw= X-Endpoint-Received: by B4 Relay for nathan.lynch@amd.com/20260410 with auth_id=728 X-Original-From: Nathan Lynch Reply-To: nathan.lynch@amd.com From: Nathan Lynch Add enough code to bind a SDXI device via the class code and map its control registers and doorbell region. All device resources are managed with devres at this point, so there is no explicit teardown path. While the SDXI specification includes a PCIe binding, the standard is intended to be independent of the underlying I/O interconnect. So the driver confines PCI-specific code to pci.c, and the rest (such as device.c, introduced here) is bus-agnostic. Hence there is some indirection: during probe, the bus code registers any matched device with the generic SDXI core, supplying the device and a sdxi_bus_ops vector. After the core associates a new sdxi_dev with the device, bus-specific initialization proceeds via the sdxi_bus_ops->init() callback. Co-developed-by: Wei Huang Signed-off-by: Wei Huang Signed-off-by: Nathan Lynch --- drivers/dma/Kconfig | 2 ++ drivers/dma/Makefile | 1 + drivers/dma/sdxi/Kconfig | 8 +++++ drivers/dma/sdxi/Makefile | 6 ++++ drivers/dma/sdxi/device.c | 26 +++++++++++++++ drivers/dma/sdxi/pci.c | 83 +++++++++++++++++++++++++++++++++++++++++++++++ drivers/dma/sdxi/sdxi.h | 38 ++++++++++++++++++++++ 7 files changed, 164 insertions(+) diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index ae6a682c9f76..3d89284e7cf8 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -762,6 +762,8 @@ source "drivers/dma/lgm/Kconfig" source "drivers/dma/loongson/Kconfig" +source "drivers/dma/sdxi/Kconfig" + source "drivers/dma/stm32/Kconfig" # clients diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile index 14aa086629d5..371927615c4a 100644 --- a/drivers/dma/Makefile +++ b/drivers/dma/Makefile @@ -84,6 +84,7 @@ obj-$(CONFIG_XGENE_DMA) += xgene-dma.o obj-$(CONFIG_ST_FDMA) += st_fdma.o obj-$(CONFIG_FSL_DPAA2_QDMA) += fsl-dpaa2-qdma/ obj-$(CONFIG_INTEL_LDMA) += lgm/ +obj-$(CONFIG_SDXI) += sdxi/ obj-y += amd/ obj-y += loongson/ diff --git a/drivers/dma/sdxi/Kconfig b/drivers/dma/sdxi/Kconfig new file mode 100644 index 000000000000..a568284cd583 --- /dev/null +++ b/drivers/dma/sdxi/Kconfig @@ -0,0 +1,8 @@ +config SDXI + tristate "SDXI support" + select DMA_ENGINE + help + Enable support for Smart Data Accelerator Interface (SDXI) + Platform Data Mover devices. SDXI is a vendor-neutral + standard for a memory-to-memory data mover and acceleration + interface. diff --git a/drivers/dma/sdxi/Makefile b/drivers/dma/sdxi/Makefile new file mode 100644 index 000000000000..f84b87d53e27 --- /dev/null +++ b/drivers/dma/sdxi/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_SDXI) += sdxi.o + +sdxi-objs += device.o + +sdxi-$(CONFIG_PCI_MSI) += pci.o diff --git a/drivers/dma/sdxi/device.c b/drivers/dma/sdxi/device.c new file mode 100644 index 000000000000..b718ce04afa0 --- /dev/null +++ b/drivers/dma/sdxi/device.c @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * SDXI hardware device driver + * + * Copyright Advanced Micro Devices, Inc. + */ + +#include +#include + +#include "sdxi.h" + +int sdxi_register(struct device *dev, const struct sdxi_bus_ops *ops) +{ + struct sdxi_dev *sdxi; + + sdxi = devm_kzalloc(dev, sizeof(*sdxi), GFP_KERNEL); + if (!sdxi) + return -ENOMEM; + + sdxi->dev = dev; + sdxi->bus_ops = ops; + dev_set_drvdata(dev, sdxi); + + return sdxi->bus_ops->init(sdxi); +} diff --git a/drivers/dma/sdxi/pci.c b/drivers/dma/sdxi/pci.c new file mode 100644 index 000000000000..9ac94d6f8b96 --- /dev/null +++ b/drivers/dma/sdxi/pci.c @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * SDXI PCI device code + * + * Copyright Advanced Micro Devices, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "sdxi.h" + +enum sdxi_mmio_bars { + SDXI_PCI_BAR_CTL_REGS = 0, + SDXI_PCI_BAR_DOORBELL = 2, +}; + +static struct pci_dev *sdxi_to_pci_dev(const struct sdxi_dev *sdxi) +{ + return to_pci_dev(sdxi->dev); +} + +static int sdxi_pci_init(struct sdxi_dev *sdxi) +{ + struct pci_dev *pdev = sdxi_to_pci_dev(sdxi); + struct device *dev = &pdev->dev; + int ret; + + ret = pcim_enable_device(pdev); + if (ret) + return dev_err_probe(dev, ret, "failed to enable device\n"); + + dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)); + + sdxi->ctrl_regs = pcim_iomap_region(pdev, SDXI_PCI_BAR_CTL_REGS, + KBUILD_MODNAME); + if (IS_ERR(sdxi->ctrl_regs)) + return dev_err_probe(dev, PTR_ERR(sdxi->ctrl_regs), + "failed to map control registers\n"); + + sdxi->dbs = pcim_iomap_region(pdev, SDXI_PCI_BAR_DOORBELL, + KBUILD_MODNAME); + if (IS_ERR(sdxi->dbs)) + return dev_err_probe(dev, PTR_ERR(sdxi->dbs), + "failed to map doorbell region\n"); + + pci_set_master(pdev); + return 0; +} + +static const struct sdxi_bus_ops sdxi_pci_ops = { + .init = sdxi_pci_init, +}; + +static int sdxi_pci_probe(struct pci_dev *pdev, + const struct pci_device_id *id) +{ + return sdxi_register(&pdev->dev, &sdxi_pci_ops); +} + +static const struct pci_device_id sdxi_id_table[] = { + { PCI_DEVICE_CLASS(PCI_CLASS_ACCELERATOR_SDXI, 0xffffff) }, + { } +}; +MODULE_DEVICE_TABLE(pci, sdxi_id_table); + +static struct pci_driver sdxi_driver = { + .name = "sdxi", + .id_table = sdxi_id_table, + .probe = sdxi_pci_probe, + .sriov_configure = pci_sriov_configure_simple, +}; + +MODULE_AUTHOR("Wei Huang"); +MODULE_AUTHOR("Nathan Lynch"); +MODULE_DESCRIPTION("SDXI PCIe interface driver"); +MODULE_LICENSE("GPL"); +module_pci_driver(sdxi_driver); diff --git a/drivers/dma/sdxi/sdxi.h b/drivers/dma/sdxi/sdxi.h new file mode 100644 index 000000000000..d4c61ca2f875 --- /dev/null +++ b/drivers/dma/sdxi/sdxi.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * SDXI device driver header + * + * Copyright Advanced Micro Devices, Inc. + */ + +#ifndef DMA_SDXI_H +#define DMA_SDXI_H + +#include +#include + +struct sdxi_dev; + +/** + * struct sdxi_bus_ops - Bus-specific methods for SDXI devices. + */ +struct sdxi_bus_ops { + /** + * @init: Map control registers and doorbell region, allocate + * IRQ ranges. Invoked before bus-agnostic SDXI + * function initialization. + */ + int (*init)(struct sdxi_dev *sdxi); +}; + +struct sdxi_dev { + struct device *dev; + void __iomem *ctrl_regs; /* virt addr of ctrl registers */ + void __iomem *dbs; /* virt addr of doorbells */ + + const struct sdxi_bus_ops *bus_ops; +}; + +int sdxi_register(struct device *dev, const struct sdxi_bus_ops *ops); + +#endif /* DMA_SDXI_H */ -- 2.54.0