From: sashiko-bot@kernel.org
To: "Bartosz Golaszewski" <bartosz.golaszewski@oss.qualcomm.com>
Cc: vkoul@kernel.org, Frank.Li@kernel.org, dmaengine@vger.kernel.org
Subject: Re: [PATCH v17 02/14] dmaengine: qcom: bam_dma: free interrupt before the clock in error path
Date: Tue, 19 May 2026 13:48:02 +0000 [thread overview]
Message-ID: <20260519134804.000F8C2BCC7@smtp.kernel.org> (raw)
In-Reply-To: <20260519-qcom-qce-cmd-descr-v17-2-53a595414b79@oss.qualcomm.com>
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] The patch fails to resolve the unclocked register access bug in `bam_dma_remove()`, resulting in a deterministic crash on device removal.
- [High] Race condition in `bam_dma_probe()` can trigger an IRQ storm resulting in a permanently disabled interrupt.
--
commit 39d4da1e9be1c385de4964ad3c6f55d2aea52136
Author: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
dmaengine: qcom: bam_dma: free interrupt before the clock in error path
This commit replaces the devres-managed IRQ allocation with manual IRQ
requesting and freeing. It ensures the interrupt is freed before
disabling the clock in the probe error path to prevent unclocked
register accesses if the IRQ fires.
Fixes: e7c0fe2a5c84 ("dmaengine: add Qualcomm BAM dma driver")
Closes: https://sashiko.dev/#/patchset/20260427-qcom-qce-cmd-descr-v16-0-945fd1cafbbc%40oss.qualcomm.com?part=2
> diff --git a/drivers/dma/qcom/bam_dma.c b/drivers/dma/qcom/bam_dma.c
> index 19116295f8325..cea44833201d6 100644
> --- a/drivers/dma/qcom/bam_dma.c
> +++ b/drivers/dma/qcom/bam_dma.c
> @@ -1302,8 +1302,7 @@ static int bam_dma_probe(struct platform_device *pdev)
> for (i = 0; i < bdev->num_channels; i++)
> bam_channel_init(bdev, &bdev->channels[i], i);
>
> - ret = devm_request_irq(bdev->dev, bdev->irq, bam_dma_irq,
> - IRQF_TRIGGER_HIGH, "bam_dma", bdev);
> + ret = request_irq(bdev->irq, bam_dma_irq, IRQF_TRIGGER_HIGH, "bam_dma", bdev);
> if (ret)
> goto err_bam_channel_exit;
This isn't a new regression, but since the goal is to safely manage the BAM
interrupt, could requesting the IRQ here before PM runtime is enabled lead
to an IRQ storm?
If an interrupt asserts after request_irq() but before pm_runtime_enable()
is called later in the probe sequence, bam_dma_irq() will execute and call
pm_runtime_get_sync().
Because PM runtime is disabled, this returns -EACCES. The handler then
returns IRQ_NONE without clearing the hardware interrupt status.
Since the interrupt is level-triggered (IRQF_TRIGGER_HIGH), the hardware
will continuously re-assert it, causing an IRQ storm until the kernel's
spurious IRQ detector permanently disables the interrupt line.
Should PM runtime be enabled and marked active before requesting the IRQ?
[ ... ]
> @@ -1379,7 +1380,7 @@ static void bam_dma_remove(struct platform_device *pdev)
> /* mask all interrupts for this execution environment */
> writel_relaxed(0, bam_addr(bdev, 0, BAM_IRQ_SRCS_MSK_EE));
>
> - devm_free_irq(bdev->dev, bdev->irq, bdev);
> + free_irq(bdev->irq, bdev);
The commit message notes that disabling the clock before freeing or masking
the interrupt can lead to unclocked BAM register accesses. Does this same
regression still exist here in bam_dma_remove()?
At the beginning of bam_dma_remove(), pm_runtime_force_suspend() is called:
static void bam_dma_remove(struct platform_device *pdev)
{
struct bam_device *bdev = platform_get_drvdata(pdev);
u32 i;
pm_runtime_force_suspend(&pdev->dev);
...
This invokes bam_dma_runtime_suspend() which explicitly disables the BAM
clock.
Immediately afterward, the driver executes the writel_relaxed() shown above
to mask interrupts. Writing to BAM hardware registers with the clock gated
will deterministically trigger a synchronous external abort (bus crash) on
Qualcomm platforms. Furthermore, free_irq() is called after the clock is
disabled, leaving the same race condition open.
To safely tear down the device, would it be better to wake the device via
pm_runtime_get_sync(), mask and free the IRQ, terminate DMA, and only then
disable PM runtime and clocks?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260519-qcom-qce-cmd-descr-v17-0-53a595414b79@oss.qualcomm.com?part=2
next prev parent reply other threads:[~2026-05-19 13:48 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-19 13:17 [PATCH v17 00/14] crypto/dmaengine: qce: introduce BAM locking and use DMA for register I/O Bartosz Golaszewski
2026-05-19 13:17 ` [PATCH v17 01/14] dmaengine: constify struct dma_descriptor_metadata_ops Bartosz Golaszewski
2026-05-19 13:17 ` [PATCH v17 02/14] dmaengine: qcom: bam_dma: free interrupt before the clock in error path Bartosz Golaszewski
2026-05-19 13:48 ` sashiko-bot [this message]
2026-05-19 13:17 ` [PATCH v17 03/14] dmaengine: qcom: bam_dma: convert tasklet to a BH workqueue Bartosz Golaszewski
2026-05-19 13:44 ` sashiko-bot
2026-05-19 13:17 ` [PATCH v17 04/14] dmaengine: qcom: bam_dma: Extend the driver's device match data Bartosz Golaszewski
2026-05-19 13:17 ` [PATCH v17 05/14] dmaengine: qcom: bam_dma: Add pipe_lock_supported flag support Bartosz Golaszewski
2026-05-19 13:17 ` [PATCH v17 06/14] dmaengine: qcom: bam_dma: add support for BAM locking Bartosz Golaszewski
2026-05-19 13:54 ` sashiko-bot
2026-05-19 13:17 ` [PATCH v17 07/14] crypto: qce - Cancel work on device detach Bartosz Golaszewski
2026-05-19 13:47 ` sashiko-bot
2026-05-19 13:17 ` [PATCH v17 08/14] crypto: qce - Include algapi.h in the core.h header Bartosz Golaszewski
2026-05-19 13:17 ` [PATCH v17 09/14] crypto: qce - Remove unused ignore_buf Bartosz Golaszewski
2026-05-19 13:48 ` sashiko-bot
2026-05-19 13:17 ` [PATCH v17 10/14] crypto: qce - Simplify arguments of devm_qce_dma_request() Bartosz Golaszewski
2026-05-19 13:17 ` [PATCH v17 11/14] crypto: qce - Use existing devres APIs in devm_qce_dma_request() Bartosz Golaszewski
2026-05-19 14:00 ` sashiko-bot
2026-05-19 13:17 ` [PATCH v17 12/14] crypto: qce - Map crypto memory for DMA Bartosz Golaszewski
2026-05-19 13:52 ` sashiko-bot
2026-05-19 13:17 ` [PATCH v17 13/14] crypto: qce - Add BAM DMA support for crypto register I/O Bartosz Golaszewski
2026-05-19 13:56 ` sashiko-bot
2026-05-19 13:17 ` [PATCH v17 14/14] crypto: qce - Communicate the base physical address to the dmaengine Bartosz Golaszewski
2026-05-19 14:17 ` sashiko-bot
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