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(unknown [172.20.64.188]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id 1FD0641609C7; Thu, 21 May 2026 15:29:26 +0800 (CST) From: Jun Guo To: peter.chen@cixtech.com, fugang.duan@cixtech.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, vkoul@kernel.org, ychuang3@nuvoton.com, schung@nuvoton.com, robin.murphy@arm.com, Frank.Li@kernel.org Cc: dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, cix-kernel-upstream@cixtech.com, linux-arm-kernel@lists.infradead.org, Jun Guo Subject: [PATCH v7 0/2] dmaengine: arm-dma350: handle shared channel IRQ wiring on sky1 Date: Thu, 21 May 2026 15:29:22 +0800 Message-Id: <20260521072924.3000282-1-jun.guo@cixtech.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SG2PEPF000B66CC:EE_|PUZPR06MB6267:EE_ Content-Type: text/plain X-MS-Office365-Filtering-Correlation-Id: 98ebc0d0-ec36-417f-afca-08deb70ab091 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|1800799024|82310400026|376014|7416014|56012099003|18002099003|921020|3023799007|5023799004; X-Microsoft-Antispam-Message-Info: 3KONVPLm4rlMDY0a9ooZWrmOP3dffoneav7XAUcY5GvsvoiWgTBmwzkq94VRXX1BUbcEx6eT5xPT2ZsakIf1St8iCX0QAe8Z6zL+7gzBBBjrv/DiRJFTMYJygd9WcNeU6zghKtlWNn9JGWM9HW41soqCVrYu12HdETlFIaNI8lalonV9F67EKbk1hUHfvX4mDw5yLTWT6FnKgEVd9oNbbNAPlWwpl8hsRbIAHV4spRyEJef7V9Wh/P64XSNEdWT0Uutrl/nOfO6UfhOXZ5sv2YjEDQUZmkxQHRSsmxPybJJZrY/kfVoYXq/S7OtswqKyBWujcxEF+551gMDbQb4fAITO8VHiF71avTC5CQWhvRk9FqNGgsWNEvnM9cLc7zN1v5rIakU249K3XRyNAQKyKRE5spewIbMVj6mEIKKRnq8v8UX9NuOnqcM11Fu/AYDRnvFv8ltF6YmszWIHvcI2fLAaid7UIEcdD9Yav3SwccHpkhakK8WSP4tuYPIbjhNwk8h6ePFnWTzd4918C2Fu86hHNTREZ12I0TQ3n08NsXfdAkPGw48yXuzffgPBmqrLTbSoH5LgZjAsB37YHrGfs7XUho2JEcVhfN3IJ0TLdTvcI3tk+mHiL3LpyJfvjYhcbQZ8OkVEIvZJVO9YCq9T/2XNi/6z20xl9mFTxrNCRe94lUFyhkgaqZGK3ppIpT7lOfSKN35XN1wV/zi0nYyLAYxVlZwvKIg+nmH67LFEw6bpuIFXWARUH3VAUtKt68nTVibQbeK/16TcOC3Stem0gw== X-Forefront-Antispam-Report: CIP:222.71.101.198;CTRY:CN;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:smtprelay.cixcomputing.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700016)(1800799024)(82310400026)(376014)(7416014)(56012099003)(18002099003)(921020)(3023799007)(5023799004);DIR:OUT;SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: adb3x4yDlw848MmGVtX0wAq3nhQjbQgFeq7QhnCgfcuOQ4kgiwmgQzJFckX2eKIksOBCaGNn6UlXdS/8WhRJRI5Y64LtKodgScAXI9OmY2pmy04eZ+V6Cr3MpH2NhG0WkWdsfkNxVxOSvOJfoWrq0o6SLShoq7NSg8uOMO1JX14g2Cn+JgFI9QY1I30mytOOqK7OBtwF0XlImnVGPqnuH0vVTlEhdV5DxhzF+V5cGSXpoGoQ0rYur/1jdzaA2vbLr1CRyL5xiyh3bNdrDQ7CVDv1RIlbifj+T1zvxZbs48E6utO1GMt+XG8yMMogVGoqdbBLW1VJJH/eO0jxOM+j9K7ToVE3ki0cZmHeaXP5Bt/UKSl7k84OxM/IzPXxsrQ2Fzcr8OsMv0SxcASr6EoL7u+RUpJRVJP4ik8VytqhF2M+hxi9Pk6YptpZkvyVgcCv X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 May 2026 07:29:27.1364 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 98ebc0d0-ec36-417f-afca-08deb70ab091 X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: SG2PEPF000B66CC.apcprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PUZPR06MB6267 This series updates DMA-350 support for the SKY1 integration where all DMA channel interrupt outputs are wired to the same GIC SPI. Patch 1 enables DMANSECCTRL.INTREN_ANYCHINTR in the driver so per-channel interrupt status is propagated even when channels share one parent IRQ line. Patch 2 adds the SKY1 DMA-350 DT node and describes the channel interrupt sources using 8 channel entries, while all entries map to the same SPI. Tested on CIX SKY1 with dmatest: % echo 2000 > /sys/module/dmatest/parameters/timeout % echo 1 > /sys/module/dmatest/parameters/iterations % echo "" > /sys/module/dmatest/parameters/channel % echo 1 > /sys/module/dmatest/parameters/run Changes in v7: - Modify the commit log format for the driver patch. Changes in v6: - Drop the dt-binding update and keep the existing 8-channel interrupt schema. - Simplify driver change to a minimal fix: enable DMANSECCTRL.INTREN_ANYCHINTR. - Update SKY1 DT node to describe 8 channel interrupt entries mapped to one SPI. Changes in v5: - Fix the formatting issue in the AI tag. - Remove the unnecessary "cix,sky1-dma-350". Changes in v4: - Reword binding text to align with kernel style. - Revise the AI attribution to the standard format. - Remove redundant links from the commit log. Changes in v3: - Rework binding compatible description to match generic-first model. - Keep interrupts schema support for both 1-IRQ and 8-IRQ topologies. - Drop SoC match-data dependency for IRQ mode selection. - Detect IRQ topology via platform_irq_count() in probe path. - Refactor IRQ handling into a shared channel handler. - Enable DMANSECCTRL.INTREN_ANYCHINTR only in combined IRQ mode. Changes in v2: - Update to kernel standards, enhance patch description, and refactor driver to use match data for hardware differentiation instead of compatible strings. Jun Guo (2): dmaengine: arm-dma350: enable ANYCH interrupt for shared IRQ wiring arm64: dts: cix: add sky1 DMA-350 node with channel IRQ entries arch/arm64/boot/dts/cix/sky1.dtsi | 14 ++++++++++++++ drivers/dma/arm-dma350.c | 9 +++++++++ 2 files changed, 23 insertions(+) -- 2.34.1