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Date: Mon, 1 Jun 2026 16:43:32 +0200
From: Christoph Hellwig <hch@lst.de>
To: Greg Ungerer <gerg@kernel.org>
Cc: Angelo Dureghello <adureghello@baylibre.com>,
	Arnd Bergmann <arnd@kernel.org>, linux-m68k@lists.linux-m68k.org,
	linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org,
	linux-can@vger.kernel.org, linux-spi@vger.kernel.org,
	Vladimir Oltean <olteanv@gmail.com>, Christoph Hellwig <hch@lst.de>
Subject: Re: [RFC 4/4] m68k: coldfire: fix non-standard readX()/writeX()
 functions
Message-ID: <20260601144332.GC4918@lst.de>
References: <20260506142644.3234270-8-gerg@kernel.org> <40aefc39-bd98-460d-8aa7-5dd79f562e0d@app.fastmail.com> <fdd6fc14-f607-4186-8db4-25de973ac322@kernel.org> <CALSJ-wCrNDv3N2Kdo0uoXsKGtp0GthJRBeYTNQA1gGE2akUWFg@mail.gmail.com> <9391b782-7727-47fa-ac37-05cd50821d35@app.fastmail.com> <CALSJ-wBRmUpjz-_ehZ0U0Gu+fPqRUeAn47E0_pwpXQa0tCNzVA@mail.gmail.com> <CALSJ-wCuZs9cBJsuOOYMEYM6xOXZbdOm_pr=70d3HRYYSYJ0KA@mail.gmail.com> <CALSJ-wDm8NoB8mF3KSx49XMSWz1vjwFhSmgJZWq8pN2pCf12mw@mail.gmail.com> <CALSJ-wDY_8SMAvKT0L6wMbH1=w5pZNmV=xyeX1REb=BMRZWj-g@mail.gmail.com> <2b532d56-dce4-4f6d-84e0-2fd87d5494f8@kernel.org>
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On Sun, May 31, 2026 at 11:42:26PM +1000, Greg Ungerer wrote:
> I don't think that is right. The way the underlying data cache is setup for
> MMU ColdFire (via the ACR/CACR registers) means that individual pages cannot
> be marked as non-cached. So coherent memory allocations are not possible -
> at least the way things are today.
>
> It would be possible to set aside a chunk of RAM at kernel startup time
> to use as a pool for coherent allocations (since it could be marked as
> non-cached via the ACR/CACR registers), but there is no code to support doing
> that today.

With CONFIG_DMA_GLOBAL_POOL there is some generic code dealing with
most of this.  But if this driver worked on coldfire in the past,
it must have been fine with non-coherent memory and could use the
non-coherent allocator.