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As a result, enable COMPILE_TEST for extra compile coverage. Assisted-by: opencode:big-pickle Signed-off-by: Rosen Penev --- drivers/dma/Kconfig | 4 ++-- drivers/dma/fsl_raid.c | 50 ++++++++++++++++++------------------------ 2 files changed, 23 insertions(+), 31 deletions(-) diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index f16bd4059d84..302021540d76 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -242,7 +242,7 @@ config FSL_QDMA config FSL_RAID tristate "Freescale RAID engine Support" - depends on FSL_SOC && !ASYNC_TX_ENABLE_CHANNEL_SWITCH + depends on (FSL_SOC && !ASYNC_TX_ENABLE_CHANNEL_SWITCH) || COMPILE_TEST select DMA_ENGINE select DMA_ENGINE_RAID help @@ -448,7 +448,7 @@ config MOXART_DMA select DMA_VIRTUAL_CHANNELS help Enable support for the MOXA ART SoC DMA controller. - + Say Y here if you enabled MMP ADMA, otherwise say N. config MPC512X_DMA diff --git a/drivers/dma/fsl_raid.c b/drivers/dma/fsl_raid.c index 99945845d8b5..dedd4a83ac72 100644 --- a/drivers/dma/fsl_raid.c +++ b/drivers/dma/fsl_raid.c @@ -114,7 +114,7 @@ static void fsl_re_issue_pending(struct dma_chan *chan) spin_lock_irqsave(&re_chan->desc_lock, flags); avail = FSL_RE_SLOT_AVAIL( - in_be32(&re_chan->jrregs->inbring_slot_avail)); + ioread32be(&re_chan->jrregs->inbring_slot_avail)); list_for_each_entry_safe(desc, _desc, &re_chan->submit_q, node) { if (!avail) @@ -127,7 +127,7 @@ static void fsl_re_issue_pending(struct dma_chan *chan) re_chan->inb_count = (re_chan->inb_count + 1) & FSL_RE_RING_SIZE_MASK; - out_be32(&re_chan->jrregs->inbring_add_job, FSL_RE_ADD_JOB(1)); + iowrite32be(FSL_RE_ADD_JOB(1), &re_chan->jrregs->inbring_add_job); avail--; } spin_unlock_irqrestore(&re_chan->desc_lock, flags); @@ -167,7 +167,7 @@ static void fsl_re_dequeue(struct tasklet_struct *t) fsl_re_cleanup_descs(re_chan); spin_lock_irqsave(&re_chan->desc_lock, flags); - count = FSL_RE_SLOT_FULL(in_be32(&re_chan->jrregs->oubring_slot_full)); + count = FSL_RE_SLOT_FULL(ioread32be(&re_chan->jrregs->oubring_slot_full)); while (count--) { found = 0; hwdesc = &re_chan->oub_ring_virt_addr[re_chan->oub_count]; @@ -192,8 +192,7 @@ static void fsl_re_dequeue(struct tasklet_struct *t) oub_count = (re_chan->oub_count + 1) & FSL_RE_RING_SIZE_MASK; re_chan->oub_count = oub_count; - out_be32(&re_chan->jrregs->oubring_job_rmvd, - FSL_RE_RMVD_JOB(1)); + iowrite32be(FSL_RE_RMVD_JOB(1), &re_chan->jrregs->oubring_job_rmvd); } spin_unlock_irqrestore(&re_chan->desc_lock, flags); } @@ -206,7 +205,7 @@ static irqreturn_t fsl_re_isr(int irq, void *data) re_chan = dev_get_drvdata((struct device *)data); - irqstate = in_be32(&re_chan->jrregs->jr_interrupt_status); + irqstate = ioread32be(&re_chan->jrregs->jr_interrupt_status); if (!irqstate) return IRQ_NONE; @@ -216,13 +215,13 @@ static irqreturn_t fsl_re_isr(int irq, void *data) * need to do something more than just crashing */ if (irqstate & FSL_RE_ERROR) { - status = in_be32(&re_chan->jrregs->jr_status); + status = ioread32be(&re_chan->jrregs->jr_status); dev_err(re_chan->dev, "chan error irqstate: %x, status: %x\n", irqstate, status); } /* Clear interrupt */ - out_be32(&re_chan->jrregs->jr_interrupt_status, FSL_RE_CLR_INTR); + iowrite32be(FSL_RE_CLR_INTR, &re_chan->jrregs->jr_interrupt_status); tasklet_schedule(&re_chan->irqtask); @@ -708,30 +707,23 @@ static int fsl_re_chan_probe(struct platform_device *ofdev, } /* Program the Inbound/Outbound ring base addresses and size */ - out_be32(&chan->jrregs->inbring_base_h, - chan->inb_phys_addr & FSL_RE_ADDR_BIT_MASK); - out_be32(&chan->jrregs->oubring_base_h, - chan->oub_phys_addr & FSL_RE_ADDR_BIT_MASK); - out_be32(&chan->jrregs->inbring_base_l, - chan->inb_phys_addr >> FSL_RE_ADDR_BIT_SHIFT); - out_be32(&chan->jrregs->oubring_base_l, - chan->oub_phys_addr >> FSL_RE_ADDR_BIT_SHIFT); - out_be32(&chan->jrregs->inbring_size, - FSL_RE_RING_SIZE << FSL_RE_RING_SIZE_SHIFT); - out_be32(&chan->jrregs->oubring_size, - FSL_RE_RING_SIZE << FSL_RE_RING_SIZE_SHIFT); + iowrite32be(chan->inb_phys_addr & FSL_RE_ADDR_BIT_MASK, &chan->jrregs->inbring_base_h); + iowrite32be(chan->oub_phys_addr & FSL_RE_ADDR_BIT_MASK, &chan->jrregs->oubring_base_h); + iowrite32be(chan->inb_phys_addr >> FSL_RE_ADDR_BIT_SHIFT, &chan->jrregs->inbring_base_l); + iowrite32be(chan->oub_phys_addr >> FSL_RE_ADDR_BIT_SHIFT, &chan->jrregs->oubring_base_l); + iowrite32be(FSL_RE_RING_SIZE << FSL_RE_RING_SIZE_SHIFT, &chan->jrregs->inbring_size); + iowrite32be(FSL_RE_RING_SIZE << FSL_RE_RING_SIZE_SHIFT, &chan->jrregs->oubring_size); /* Read LIODN value from u-boot */ - status = in_be32(&chan->jrregs->jr_config_1) & FSL_RE_REG_LIODN_MASK; + status = ioread32be(&chan->jrregs->jr_config_1) & FSL_RE_REG_LIODN_MASK; /* Program the CFG reg */ - out_be32(&chan->jrregs->jr_config_1, - FSL_RE_CFG1_CBSI | FSL_RE_CFG1_CBS0 | status); + iowrite32be(FSL_RE_CFG1_CBSI | FSL_RE_CFG1_CBS0 | status, &chan->jrregs->jr_config_1); dev_set_drvdata(chandev, chan); /* Enable RE/CHAN */ - out_be32(&chan->jrregs->jr_command, FSL_RE_ENABLE); + iowrite32be(FSL_RE_ENABLE, &chan->jrregs->jr_command); return 0; @@ -768,15 +760,15 @@ static int fsl_re_probe(struct platform_device *ofdev) return -EBUSY; /* Program the RE mode */ - out_be32(&re_priv->re_regs->global_config, FSL_RE_NON_DPAA_MODE); + iowrite32be(FSL_RE_NON_DPAA_MODE, &re_priv->re_regs->global_config); /* Program Galois Field polynomial */ - out_be32(&re_priv->re_regs->galois_field_config, FSL_RE_GFM_POLY); + iowrite32be(FSL_RE_GFM_POLY, &re_priv->re_regs->galois_field_config); dev_info(dev, "version %x, mode %x, gfp %x\n", - in_be32(&re_priv->re_regs->re_version_id), - in_be32(&re_priv->re_regs->global_config), - in_be32(&re_priv->re_regs->galois_field_config)); + ioread32be(&re_priv->re_regs->re_version_id), + ioread32be(&re_priv->re_regs->global_config), + ioread32be(&re_priv->re_regs->galois_field_config)); dma_dev = &re_priv->dma_dev; dma_dev->dev = dev; -- 2.54.0