From: Rosen Penev <rosenp@gmail.com>
To: dmaengine@vger.kernel.org
Cc: Vinod Koul <vkoul@kernel.org>, Frank Li <Frank.Li@kernel.org>,
Thomas Petazzoni <thomas.petazzoni@free-electrons.com>,
Gregory CLEMENT <gregory.clement@bootlin.com>,
Marcin Wojtas <mw@semihalf.com>, Rob Herring <robh@kernel.org>,
linux-kernel@vger.kernel.org (open list)
Subject: [PATCHv2 8/9] dmaengine: mv_xor: allocate dummy buffers with dmam_alloc_coherent
Date: Thu, 11 Jun 2026 14:07:20 -0700 [thread overview]
Message-ID: <20260611210721.81979-9-rosenp@gmail.com> (raw)
In-Reply-To: <20260611210721.81979-1-rosenp@gmail.com>
Replace the streaming DMA mappings for the dummy interrupt-operation
buffers with coherent allocations. The embedded char arrays in the
channel struct shared cachelines with other members, so dma_map_single
could corrupt adjacent data during cache maintenance. These buffers
are never touched by the CPU, so coherent memory is the correct choice.
The old DMA directions were also reversed: dummy_src is read by the
XOR engine (should be DMA_TO_DEVICE) and dummy_dst is written by it
(should be DMA_FROM_DEVICE). Coherent allocations are semantically
directionless, sidestepping the issue entirely.
With dmam_alloc_coherent managing the lifetime the old dma_unmap_single
calls and the error-path labels in mv_xor_channel_add are no longer
needed.
Assisted-by: opencode:big-pickle
Signed-off-by: Rosen Penev <rosenp@gmail.com>
---
drivers/dma/mv_xor.c | 50 ++++++++++++++------------------------------
drivers/dma/mv_xor.h | 4 ++--
2 files changed, 18 insertions(+), 36 deletions(-)
diff --git a/drivers/dma/mv_xor.c b/drivers/dma/mv_xor.c
index 0c159b9e9216..255df2dd9c71 100644
--- a/drivers/dma/mv_xor.c
+++ b/drivers/dma/mv_xor.c
@@ -1029,7 +1029,6 @@ mv_chan_xor_self_test(struct mv_xor_chan *mv_chan)
static int mv_xor_channel_remove(struct mv_xor_chan *mv_chan)
{
struct dma_chan *chan, *_chan;
- struct device *dev = mv_chan->dmadev.dev;
mv_chan_mask_interrupts(mv_chan);
mv_chan_disable(mv_chan);
@@ -1037,11 +1036,6 @@ static int mv_xor_channel_remove(struct mv_xor_chan *mv_chan)
dma_async_device_unregister(&mv_chan->dmadev);
- dma_unmap_single(dev, mv_chan->dummy_src_addr,
- MV_XOR_MIN_BYTE_COUNT, DMA_FROM_DEVICE);
- dma_unmap_single(dev, mv_chan->dummy_dst_addr,
- MV_XOR_MIN_BYTE_COUNT, DMA_TO_DEVICE);
-
list_for_each_entry_safe(chan, _chan, &mv_chan->dmadev.channels,
device_node) {
list_del(&chan->device_node);
@@ -1055,9 +1049,9 @@ mv_xor_channel_add(struct mv_xor_device *xordev,
struct platform_device *pdev,
int idx, dma_cap_mask_t cap_mask, int irq)
{
- int ret = 0;
struct mv_xor_chan *mv_chan;
struct dma_device *dma_dev;
+ int ret;
mv_chan = devm_kzalloc(&pdev->dev, sizeof(*mv_chan), GFP_KERNEL);
if (!mv_chan)
@@ -1089,19 +1083,18 @@ mv_xor_channel_add(struct mv_xor_device *xordev,
/*
* These source and destination dummy buffers are used to implement
* a DMA_INTERRUPT operation as a minimum-sized XOR operation.
- * Hence, we only need to map the buffers at initialization-time.
+ * Hence, we only need to allocate the buffers at initialization-time.
+ * The XOR engine reads from dummy_src and writes to dummy_dst.
*/
- mv_chan->dummy_src_addr = dma_map_single(dma_dev->dev,
- mv_chan->dummy_src, MV_XOR_MIN_BYTE_COUNT, DMA_FROM_DEVICE);
- if (dma_mapping_error(dma_dev->dev, mv_chan->dummy_src_addr))
+ mv_chan->dummy_src = dmam_alloc_coherent(&pdev->dev, MV_XOR_MIN_BYTE_COUNT,
+ &mv_chan->dummy_src_addr, GFP_KERNEL);
+ if (!mv_chan->dummy_src)
return ERR_PTR(-ENOMEM);
- mv_chan->dummy_dst_addr = dma_map_single(dma_dev->dev,
- mv_chan->dummy_dst, MV_XOR_MIN_BYTE_COUNT, DMA_TO_DEVICE);
- if (dma_mapping_error(dma_dev->dev, mv_chan->dummy_dst_addr)) {
- ret = -ENOMEM;
- goto err_unmap_src;
- }
+ mv_chan->dummy_dst = dmam_alloc_coherent(&pdev->dev, MV_XOR_MIN_BYTE_COUNT,
+ &mv_chan->dummy_dst_addr, GFP_KERNEL);
+ if (!mv_chan->dummy_dst)
+ return ERR_PTR(-ENOMEM);
/* allocate coherent memory for hardware descriptors
@@ -1111,10 +1104,8 @@ mv_xor_channel_add(struct mv_xor_device *xordev,
mv_chan->dma_desc_pool_virt =
dmam_alloc_attrs(&pdev->dev, MV_XOR_POOL_SIZE, &mv_chan->dma_desc_pool,
GFP_KERNEL, DMA_ATTR_WRITE_COMBINE);
- if (!mv_chan->dma_desc_pool_virt) {
- ret = -ENOMEM;
- goto err_unmap_dst;
- }
+ if (!mv_chan->dma_desc_pool_virt)
+ return ERR_PTR(-ENOMEM);
/* discover transaction capabilities from the platform data */
dma_dev->cap_mask = cap_mask;
@@ -1143,7 +1134,7 @@ mv_xor_channel_add(struct mv_xor_device *xordev,
ret = devm_request_irq(&pdev->dev, mv_chan->irq, mv_xor_interrupt_handler,
0, dev_name(&pdev->dev), mv_chan);
if (ret)
- goto err_unmap_dst;
+ return ERR_PTR(ret);
mv_chan_unmask_interrupts(mv_chan);
@@ -1158,14 +1149,14 @@ mv_xor_channel_add(struct mv_xor_device *xordev,
ret = mv_chan_memcpy_self_test(mv_chan);
dev_dbg(&pdev->dev, "memcpy self test returned %d\n", ret);
if (ret)
- goto err_unmap_dst;
+ return ERR_PTR(ret);
}
if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
ret = mv_chan_xor_self_test(mv_chan);
dev_dbg(&pdev->dev, "xor self test returned %d\n", ret);
if (ret)
- goto err_unmap_dst;
+ return ERR_PTR(ret);
}
dev_info(&pdev->dev, "Marvell XOR (%s): ( %s%s%s)\n",
@@ -1176,18 +1167,9 @@ mv_xor_channel_add(struct mv_xor_device *xordev,
ret = dma_async_device_register(dma_dev);
if (ret)
- goto err_unmap_dst;
+ return ERR_PTR(ret);
return mv_chan;
-
-err_unmap_dst:
- dma_unmap_single(dma_dev->dev, mv_chan->dummy_dst_addr,
- MV_XOR_MIN_BYTE_COUNT, DMA_TO_DEVICE);
-err_unmap_src:
- dma_unmap_single(dma_dev->dev, mv_chan->dummy_src_addr,
- MV_XOR_MIN_BYTE_COUNT, DMA_FROM_DEVICE);
-
- return ERR_PTR(ret);
}
static void
diff --git a/drivers/dma/mv_xor.h b/drivers/dma/mv_xor.h
index c87cefd38a07..666c72e457d6 100644
--- a/drivers/dma/mv_xor.h
+++ b/drivers/dma/mv_xor.h
@@ -120,8 +120,8 @@ struct mv_xor_chan {
int slots_allocated;
struct tasklet_struct irq_tasklet;
int op_in_desc;
- char dummy_src[MV_XOR_MIN_BYTE_COUNT];
- char dummy_dst[MV_XOR_MIN_BYTE_COUNT];
+ void *dummy_src;
+ void *dummy_dst;
dma_addr_t dummy_src_addr, dummy_dst_addr;
u32 saved_config_reg, saved_int_mask_reg;
--
2.54.0
next prev parent reply other threads:[~2026-06-11 21:07 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-11 21:07 [PATCHv2 0/9] dma: mv_xor: convert to devm resource management Rosen Penev
2026-06-11 21:07 ` [PATCHv2 1/9] dmaengine: mv_xor: initialize chan state before requesting IRQ Rosen Penev
2026-06-11 21:20 ` sashiko-bot
2026-06-11 21:07 ` [PATCHv2 2/9] dmaengine: mv_xor: fix use-after-free in probe error path Rosen Penev
2026-06-11 21:24 ` sashiko-bot
2026-06-11 21:07 ` [PATCHv2 3/9] dmaengine: mv_xor: bound maximum channels for Armada 37xx Rosen Penev
2026-06-11 21:22 ` sashiko-bot
2026-06-11 21:07 ` [PATCHv2 4/9] dmaengine: mv_xor: abort channel before freeing resources on timeout Rosen Penev
2026-06-11 21:07 ` [PATCHv2 5/9] dmaengine: mv_xor: use devm_clk_get_optional_enabled Rosen Penev
2026-06-11 21:19 ` sashiko-bot
2026-06-11 21:07 ` [PATCHv2 6/9] dmaengine: mv_xor: switch to of_irq_get() Rosen Penev
2026-06-11 21:07 ` [PATCHv2 7/9] dmaengine: mv_xor: use devm for dma pool and irq Rosen Penev
2026-06-11 21:22 ` sashiko-bot
2026-06-11 21:07 ` Rosen Penev [this message]
2026-06-11 21:07 ` [PATCHv2 9/9] dmaengine: mv_xor: add missing platform remove function Rosen Penev
2026-06-11 21:19 ` sashiko-bot
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