From: sashiko-bot@kernel.org
To: "Linus Walleij" <linusw@kernel.org>
Cc: robh@kernel.org, dri-devel@lists.freedesktop.org,
conor+dt@kernel.org, devicetree@vger.kernel.org,
Frank.Li@kernel.org, vkoul@kernel.org, dmaengine@vger.kernel.org
Subject: Re: [PATCH 05/11] ARM: dts: ux500: Add power domains
Date: Thu, 18 Jun 2026 05:14:51 +0000 [thread overview]
Message-ID: <20260618051451.6F0AA1F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260618-ux500-power-domains-v7-1-v1-5-eb5e50b1a588@kernel.org>
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] The `clocks` node is incorrectly assigned to `DOMAIN_VPLL` instead of `DOMAIN_VAPE` and includes an unresolved `CHECKME` comment.
- [Medium] Adding `power-domains` to nodes whose binding schemas do not allow it will cause `dtbs_check` validation errors.
--
commit 57cdb12b349af07637860b10a8f8232b9e2930bc
Author: Linus Walleij <linusw@kernel.org>
ARM: dts: ux500: Add power domains
Add the actual power domains to all the SoC peripherals.
> diff --git a/arch/arm/boot/dts/st/ste-dbx5x0.dtsi b/arch/arm/boot/dts/st/ste-dbx5x0.dtsi
> index d76a65da70111..a6fef302c994e 100644
> --- a/arch/arm/boot/dts/st/ste-dbx5x0.dtsi
> +++ b/arch/arm/boot/dts/st/ste-dbx5x0.dtsi
[ ... ]
> @@ -334,6 +340,7 @@ L2: cache-controller {
> compatible = "arm,pl310-cache";
> reg = <0xa0412000 0x1000>;
> interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
> + power-domains = <&pm_domains DOMAIN_VARM>;
[Severity: Medium]
Will adding power-domains here cause dtbs_check validation errors?
The l2c2x0.yaml binding schema (along with others modified in this patch like
arm/pmu.yaml, stericsson,u8500-clks.yaml, arm,twd-timer.yaml,
arm,twd-wdt.yaml, and ste,mcde.yaml) does not include power-domains in its
list of allowed properties.
Do these bindings need to be updated to document the power-domains capability
before it can be used?
> cache-unified;
> cache-level = <2>;
> };
[ ... ]
> @@ -357,6 +365,7 @@ clocks {
> reg = <0x8012f000 0x1000>, <0x8011f000 0x1000>,
> <0x8000f000 0x1000>, <0xa03ff000 0x1000>,
> <0xa03cf000 0x1000>;
> + power-domains = <&pm_domains DOMAIN_VPLL>; /* CHECKME: correct domain? */
[Severity: High]
Should this be DOMAIN_VAPE instead of DOMAIN_VPLL?
The PRCC registers mapped here for peripheral groups 1, 2, 3, 5, and 6 reside
in the VAPE power domain alongside the peripherals they clock.
If the clock controller is assigned to DOMAIN_VPLL, the power domain framework
won't guarantee DOMAIN_VAPE is powered on when accessing these registers,
which could cause a synchronous external abort.
Also, is the CHECKME comment intended to be resolved before merging?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260618-ux500-power-domains-v7-1-v1-0-eb5e50b1a588@kernel.org?part=5
next prev parent reply other threads:[~2026-06-18 5:14 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-18 5:00 [PATCH 00/11] pmdomain: st: ux500: Implement ux500 power domains Linus Walleij
2026-06-18 5:00 ` [PATCH 01/11] dt-bindings: power: Convert Ux500 PM domains to schema Linus Walleij
2026-06-18 5:07 ` sashiko-bot
2026-06-18 5:00 ` [PATCH 02/11] dt-bindings: Add the actual power domains on U8500 Linus Walleij
2026-06-18 5:00 ` [PATCH 03/11] pmdomain: st: ux500: Implement more power domains Linus Walleij
2026-06-18 5:10 ` sashiko-bot
2026-06-18 5:00 ` [PATCH 04/11] ARM: dts: ux500: Rename power domains node Linus Walleij
2026-06-18 5:00 ` [PATCH 05/11] ARM: dts: ux500: Add power domains Linus Walleij
2026-06-18 5:14 ` sashiko-bot [this message]
2026-06-18 5:00 ` [PATCH 06/11] pmdomain: st: ux500: Control DB8500 EPODs Linus Walleij
2026-06-18 5:14 ` sashiko-bot
2026-06-18 5:00 ` [PATCH 07/11] drm/mcde: Use power domain for display power Linus Walleij
2026-06-18 5:11 ` sashiko-bot
2026-06-18 5:00 ` [PATCH 08/11] dmaengine: ste_dma40: Use power domain for LCLA SRAM Linus Walleij
2026-06-18 5:15 ` sashiko-bot
2026-06-18 5:00 ` [PATCH 09/11] regulator: db8500-prcmu: Remove EPOD regulators Linus Walleij
2026-06-18 5:15 ` sashiko-bot
2026-06-18 5:00 ` [PATCH 10/11] regulator: db8500: Add power domain regulators Linus Walleij
2026-06-18 5:23 ` sashiko-bot
2026-06-18 5:00 ` [PATCH 11/11] ARM: dts: ux500: Remove DB8500 EPOD regulators Linus Walleij
2026-06-18 7:20 ` sashiko-bot
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20260618051451.6F0AA1F000E9@smtp.kernel.org \
--to=sashiko-bot@kernel.org \
--cc=Frank.Li@kernel.org \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=dmaengine@vger.kernel.org \
--cc=dri-devel@lists.freedesktop.org \
--cc=linusw@kernel.org \
--cc=robh@kernel.org \
--cc=sashiko-reviews@lists.linux.dev \
--cc=vkoul@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox