From: sashiko-bot@kernel.org
To: "Suraj Gupta" <suraj.gupta2@amd.com>
Cc: Frank.Li@kernel.org, dmaengine@vger.kernel.org, vkoul@kernel.org
Subject: Re: [PATCH v3 1/3] dmaengine: xilinx_dma: Fix channel idle state management in AXIDMA and MCDMA interrupt handlers
Date: Fri, 26 Jun 2026 09:47:21 +0000 [thread overview]
Message-ID: <20260626094721.9FC9B1F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260626092656.1563871-2-suraj.gupta2@amd.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
Pre-existing issues:
- [High] The patch claims to fix a race condition for MCDMA channels by conditionally marking the channel as idle only when `active_list` is empty. However, this fix is entirely ineffective because `xilinx_dma_complete_descriptor()` unconditionally empties `active_list` for MCDMA.
--
commit fef85fe49f3788eecfb93a71efa6536e69b799c0
Author: Suraj Gupta <suraj.gupta2@amd.com>
dmaengine: xilinx_dma: Fix channel idle state management in AXIDMA and MCDMA interrupt handlers
This patch fixes a race condition in AXIDMA and MCDMA irq handlers by only
marking the channel idle and starting a new transfer when the active list is
empty.
> diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c
> index 404235c173538..ca396b7097427 100644
> --- a/drivers/dma/xilinx/xilinx_dma.c
> +++ b/drivers/dma/xilinx/xilinx_dma.c
> @@ -1893,8 +1893,10 @@ static irqreturn_t xilinx_mcdma_irq_handler(int irq, void *data)
> if (status & XILINX_MCDMA_IRQ_IOC_MASK) {
> spin_lock(&chan->lock);
> xilinx_dma_complete_descriptor(chan);
> - chan->idle = true;
> - chan->start_transfer(chan);
> + if (list_empty(&chan->active_list)) {
[Severity: High]
This is a pre-existing issue, but does this check actually prevent the race
condition for MCDMA channels?
Looking at xilinx_dma_complete_descriptor(), the hardware completion check
is restricted to AXIDMA:
drivers/dma/xilinx/xilinx_dma.c:xilinx_dma_complete_descriptor() {
list_for_each_entry_safe(desc, next, &chan->active_list, node) {
if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
...
if (!(seg->hw.status & XILINX_DMA_BD_COMP_MASK) && chan->has_sg)
break;
}
...
list_del(&desc->node);
...
}
}
Because MCDMA descriptors are unconditionally unlinked from active_list
regardless of their actual hardware completion status, active_list will
always be empty after xilinx_dma_complete_descriptor() returns.
Will this cause the new idle check to always evaluate to true for MCDMA,
leaving the race condition unaddressed for those channels?
> + chan->idle = true;
> + chan->start_transfer(chan);
> + }
> spin_unlock(&chan->lock);
> }
[ ... ]
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260626092656.1563871-1-suraj.gupta2@amd.com?part=1
next prev parent reply other threads:[~2026-06-26 9:47 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-26 9:26 [PATCH v3 0/3] dmaengine: xilinx_dma: Fixes and optimizations for AXIDMA and MCDMA channel management Suraj Gupta
2026-06-26 9:26 ` [PATCH v3 1/3] dmaengine: xilinx_dma: Fix channel idle state management in AXIDMA and MCDMA interrupt handlers Suraj Gupta
2026-06-26 9:47 ` sashiko-bot [this message]
2026-06-26 10:40 ` Gupta, Suraj
2026-06-27 16:29 ` Pandey, Radhey Shyam
2026-06-26 9:26 ` [PATCH v3 2/3] dmaengine: xilinx_dma: Enable transfer chaining for AXIDMA and MCDMA by removing idle restriction Suraj Gupta
2026-06-26 9:48 ` sashiko-bot
2026-06-26 10:45 ` Gupta, Suraj
2026-06-26 13:00 ` Folker Schwesinger
2026-06-27 16:29 ` Pandey, Radhey Shyam
2026-06-26 9:26 ` [PATCH v3 3/3] dmaengine: xilinx_dma: Optimize control register write and channel start logic for AXIDMA and MCDMA in corresponding start_transfer() Suraj Gupta
2026-06-27 16:32 ` Pandey, Radhey Shyam
2026-07-02 16:03 ` [PATCH v3 0/3] dmaengine: xilinx_dma: Fixes and optimizations for AXIDMA and MCDMA channel management Vinod Koul
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