Re: [PATCH v6 02/11] arm64: dts: qcom: Add QUPv3 configuration for Shikra

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] Missing `interrupts` property for the `uart0` (qcom,geni-debug-uart) node.
- [Medium] The wakeup interrupt for uart2 on the RX pin (GPIO 9) is configured as IRQ_TYPE_LEVEL_HIGH instead of IRQ_TYPE_EDGE_FALLING.
--

--- Patch [2]: [PATCH v6 02/11] arm64: dts: qcom: Add QUPv3 configuration for Shikra ---
commit 1c9c89a1544a0e5440dc4a0a7e665dfb65d85dc8
Author: Xueyao An <xueyao.an@oss.qualcomm.com>

arm64: dts: qcom: Add QUPv3 configuration for Shikra

This commit adds device tree support for QUPv3 serial engine protocols on
the Qualcomm Shikra platform. It defines 10 QUP serial engines under a single
wrapper, with support for GPI DMA engines.

> diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
> index 4e5bc9e17c8ed..f0fb55b9deb90 100644
> --- a/arch/arm64/boot/dts/qcom/shikra.dtsi
> +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
[ ... ]
> @@ -613,10 +896,75 @@ qupv3_0: geniqup@4ac0000 {
[ ... ]
>  			uart0: serial@4a80000 {
>  				compatible = "qcom,geni-debug-uart";
>  				reg = <0x0 0x04a80000 0x0 0x4000>;

[Severity: High]
Does this node need an interrupts property? The qcom,geni-debug-uart binding
requires it, and qcom_geni_serial will fail to probe if it's missing (it calls
platform_get_irq(pdev, 0)). Since it shares SE0 with i2c0 and spi0, should
this be <GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH 0>?

[ ... ]
> @@ -638,6 +986,609 @@ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
[ ... ]
> +			uart2: serial@4a88000 {
> +				compatible = "qcom,geni-uart";
> +				reg = <0x0 0x04a88000 0x0 0x4000>;
> +
> +				interrupts-extended = <&intc GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH 0>,
> +						      <&tlmm 9 IRQ_TYPE_LEVEL_HIGH>;

[Severity: Medium]
Is IRQ_TYPE_LEVEL_HIGH correct for the tlmm 9 wakeup interrupt? UART RX lines
idle HIGH and transition LOW on the start bit. Using a level high trigger
could cause an interrupt storm when the line is idle, or prevent low-power
states. Should this be IRQ_TYPE_EDGE_FALLING instead?

> +
> +				clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
> +				clock-names = "se";

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260714-shikra-dt-m1-v6-0-bee265d3499b@oss.qualcomm.com?part=2