Re: [PATCH v2 3/3] dmaengine: dw-edma: Add changes to support Channel Separation

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:

Pre-existing issues:
- [High] eDMA/HDMA register base address missing capability offset
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--- Patch [3]: [PATCH v2 3/3] dmaengine: dw-edma: Add changes to support Channel Separation ---
commit d8b9ebd109653d1219284d3ab6408816a9dc7745
Author: Devendra K Verma <devverma@amd.com>

dmaengine: dw-edma: Add changes to support Channel Separation

This commit updates the driver to support configurable DMA channel register
space separation. It modifies channel register base address calculations to
use a dynamic separation size instead of a fixed layout, and removes unused
legacy register layout structures.

> diff --git a/drivers/dma/dw-edma/dw-edma-pcie.c b/drivers/dma/dw-edma/dw-edma-pcie.c
> index d0f209082878d..f2a9ae8d0f3c4 100644
> --- a/drivers/dma/dw-edma/dw-edma-pcie.c
> +++ b/drivers/dma/dw-edma/dw-edma-pcie.c

[ ... ]

> @@ -437,6 +440,7 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev,
>  	chip->nr_irqs = nr_irqs;
>  	chip->ops = &dw_edma_pcie_plat_ops;
>  	chip->cfg_non_ll = non_ll;
> +	chip->ch_sep_sz = vsec_data->ch_sep_sz;
>  
>  	chip->ll_wr_cnt = vsec_data->wr_ch_cnt;
>  	chip->ll_rd_cnt = vsec_data->rd_ch_cnt;

[Severity: High]
This is a pre-existing issue, but does dw_edma_pcie_probe() assign the wrong
MMIO base offset to chip->reg_base?

Just below this hunk in dw_edma_pcie_probe(), the code assigns:

    chip->reg_base = pcim_iomap_table(pdev)[vsec_data->rg.bar];
    if (!chip->reg_base)
        return -ENOMEM;

It appears the vsec_data->rg.off capability offset is never added to this base
address. Without adding the offset, won't all subsequent eDMA/HDMA register
accesses target the wrong MMIO locations (offset 0 of the BAR instead of the
specified offset like 4KB), potentially triggering bus faults or preventing
the DMA hardware from initializing?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260728091744.1086942-1-devverma@amd.com?part=3