From: Chaithanya Lagisetty <nagachaithanya9911@gmail.com>
To: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>,
Vinod Koul <vkoul@kernel.org>
Cc: Frank Li <Frank.Li@kernel.org>,
Chaithanya Lagisetty <nagachaithanya9911@gmail.com>,
dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH] dmaengine: dw-axi-dmac: fix clock imbalance in resume error path
Date: Thu, 13 Aug 2026 10:54:32 +0000 [thread overview]
Message-ID: <20260813105432.2577322-1-nagachaithanya9911@gmail.com> (raw)
axi_dma_resume() enables cfgr_clk and then core_clk. If enabling
core_clk fails, the function returns the error without disabling
cfgr_clk, which was already enabled, leaving the clock refcount
unbalanced.
Disable cfgr_clk on the core_clk enable failure path.
Fixes: 1fe20f1b8454 ("dmaengine: Introduce DW AXI DMAC driver")
Signed-off-by: Chaithanya Lagisetty <nagachaithanya9911@gmail.com>
---
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index bcefaff03b5c..9db8993e0bc6 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -1335,8 +1335,10 @@ static int axi_dma_resume(struct axi_dma_chip *chip)
return ret;
ret = clk_prepare_enable(chip->core_clk);
- if (ret < 0)
+ if (ret < 0) {
+ clk_disable_unprepare(chip->cfgr_clk);
return ret;
+ }
axi_dma_enable(chip);
axi_dma_irq_enable(chip);
--
2.43.0
next reply other threads:[~2026-08-13 10:54 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-13 10:54 Chaithanya Lagisetty [this message]
2026-08-13 11:07 ` [PATCH] dmaengine: dw-axi-dmac: fix clock imbalance in resume error path sashiko-bot
2026-08-13 16:37 ` Frank Li
2026-08-16 5:48 ` [PATCH v2] dmaengine: dw-axi-dmac: convert clock handling to clk_bulk API Chaithanya Lagisetty
2026-08-16 6:05 ` sashiko-bot
2026-08-19 19:22 ` Frank Li
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