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Wed, 09 Sep 2026 16:46:48 -0700 (PDT) Received: from ryzen.lan ([2601:644:8000:7a86::e35]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-39d7e92b776sm512885a91.17.2026.09.09.16.46.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Sep 2026 16:46:47 -0700 (PDT) From: Rosen Penev To: dmaengine@vger.kernel.org Cc: Vinod Koul , Frank Li , Maciej Sosnowski , Lennert Buytenhek , Dan Williams , Saeed Bishara , Nicolas Pitre , linux-kernel@vger.kernel.org (open list) Subject: [PATCH] dmaengine: mv_xor: add missing dma_wmb() barriers before descriptor chain start Date: Wed, 9 Sep 2026 16:46:46 -0700 Message-ID: <20260909234646.102344-1-rosenp@gmail.com> X-Mailer: git-send-email 2.55.0 Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The descriptor data written to coherent memory must be visible to the DMA engine before the HW registers that trigger processing are written. Add a dma_wmb() before mv_chan_set_next_descriptor() in mv_chan_start_new_chain() to order descriptor fields before the descriptor-pointer write. Add a dma_wmb() after mv_desc_set_next_desc() in mv_chan_handle_chain_append() to order the chain link write before the subsequent check of the current-descriptor register. Without the barrier the hardware may observe stale descriptor data. Fixes: ff7b04796d98 ("DMA engine driver for Marvell XOR engine") Assisted-by: opencode:big-pickle Signed-off-by: Rosen Penev --- drivers/dma/mv_xor.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/dma/mv_xor.c b/drivers/dma/mv_xor.c index 24f22db5dfa1..6db7dafac9c8 100644 --- a/drivers/dma/mv_xor.c +++ b/drivers/dma/mv_xor.c @@ -181,6 +181,7 @@ static void mv_chan_start_new_chain(struct mv_xor_chan *mv_chan, dev_dbg(mv_chan_to_devp(mv_chan), "%s %d: sw_desc %p\n", __func__, __LINE__, sw_desc); + dma_wmb(); /* set the hardware chain */ mv_chan_set_next_descriptor(mv_chan, sw_desc->async_tx.phys); @@ -409,6 +410,7 @@ mv_xor_tx_submit(struct dma_async_tx_descriptor *tx) /* fix up the hardware chain */ mv_desc_set_next_desc(old_chain_tail, sw_desc->async_tx.phys); + dma_wmb(); /* if the channel is not busy */ if (!mv_chan_is_busy(mv_chan)) { -- 2.55.0