From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A614D370AEB; Sat, 19 Sep 2026 22:22:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789856540; cv=none; b=RM1+A5Hg3u2m1ES6tykgM1lWlsFSkOXqhuV+MQ6P7Skh6RBvrKfDJLG3WmGJZuIujkBKKapwjjf/GV/AuVb4aXkRZ3/GmrImnV8+/TQoO1gqQKBTbZNAP9V8TfdpTlE4w4/qRPUpzimMxURDCgVRhwrfdY/huElkwfbjLprWvFc= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789856540; c=relaxed/simple; bh=6Ew79j6hMvJCjmqap1EEUitXbIbL7CxWBT0atyFYuBg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=tDB2xBl5/ReX0pJCrc7KdnRbuF3WLlmyx2yVHKo0MSSdFlZDgWzjnTqG8XJUsmHCuN2euDjhAJLcIGYOCzfyD62phMdG2qFJeZYq3W9HiZuFyUXHpZZDnFKEDeMTbeFgoTMrYbNyvMYIcN/2a2BkDswq32gjRtpwrfyz1Tcp9SY= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=FFq9OWih; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="FFq9OWih" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5C8B11F00893; Sat, 19 Sep 2026 22:22:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1789856539; bh=/09QadBHomxpcxK74miqEkVw76R4Y2u+0IXs891ae5Y=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=FFq9OWihmPU7apYZD9vPPmIqNBqvXs9Tnz65zd4NlyH6pxo85fBpResS/v11+YH1l jUufXG33isg0xF/OCR9eEzyI68ptnkd2kRlIabzwnVoXmuTMp9316ndNwd90VBRnoG 2G5/rjgQ0lPOcI3QYwWCnrcvNfvK/Jj8AY8+1b1fsphmcP0wfiGbzCLTqdu/4afvc9 Gw3LNTWBYn7YpXnFblWtGHgcCTlyZxPQI6L0pMfXEgK84NCDXCjMwlHvM/lQn3aJGi TV//L0E5u0vrgdLLGd1ldjp2VtwmM+uQ1GVhhTGhXx2vs8zxUtKixf3b5XDjFfSqJn hasiWyTifqH5g== From: Linus Walleij Date: Sun, 20 Sep 2026 00:22:12 +0200 Subject: [PATCH v4 01/23] dmaengine: ste_dma40: Fix physical cyclic capability Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260920-dma40-fixes-v4-1-d751b2d9c23f@kernel.org> References: <20260920-dma40-fixes-v4-0-d751b2d9c23f@kernel.org> In-Reply-To: <20260920-dma40-fixes-v4-0-d751b2d9c23f@kernel.org> To: Vinod Koul , Frank Li Cc: dmaengine@vger.kernel.org, phone-devel@vger.kernel.org, Linus Walleij X-Mailer: b4 0.14.3 d40_dmaengine_init() configures dma_both for physical channels that can handle both slave and memcpy transfers. Physical DMA40 channel setup has supported cyclic LLIs since cyclic transfer support was added, but the DMA_CYCLIC capability is set on dma_slave a second time instead of dma_both. Set DMA_CYCLIC on dma_both so d40_ops_init() installs device_prep_dma_cyclic and physical channels advertise cyclic support. Fixes: 0c842b551063 ("dma40: cyclic xfer support") Assisted-by: LLM Signed-off-by: Linus Walleij --- drivers/dma/ste_dma40.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c index 0d9ffa3e2663..e4d689c9eba8 100644 --- a/drivers/dma/ste_dma40.c +++ b/drivers/dma/ste_dma40.c @@ -2897,7 +2897,7 @@ static int __init d40_dmaengine_init(struct d40_base *base, dma_cap_zero(base->dma_both.cap_mask); dma_cap_set(DMA_SLAVE, base->dma_both.cap_mask); dma_cap_set(DMA_MEMCPY, base->dma_both.cap_mask); - dma_cap_set(DMA_CYCLIC, base->dma_slave.cap_mask); + dma_cap_set(DMA_CYCLIC, base->dma_both.cap_mask); d40_ops_init(base, &base->dma_both); err = dmaenginem_async_device_register(&base->dma_both); -- 2.55.0