From: Md Sadre Alam <quic_mdalam@quicinc.com>
To: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>,
<broonie@kernel.org>, <robh@kernel.org>, <krzk+dt@kernel.org>,
<conor+dt@kernel.org>, <andersson@kernel.org>,
<konradybcio@kernel.org>, <vkoul@kernel.org>,
<linux-arm-msm@vger.kernel.org>, <linux-spi@vger.kernel.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<dmaengine@vger.kernel.org>
Cc: <quic_varada@quicinc.com>
Subject: Re: [PATCH 3/9] dma: qcom: bam_dma: Fix command element mask field for BAM v1.6.0+
Date: Fri, 19 Sep 2025 11:26:55 +0530 [thread overview]
Message-ID: <2394e63f-1df7-764e-5489-3567065707a1@quicinc.com> (raw)
In-Reply-To: <c5d5c026-3240-4828-b9b3-455f057fb041@oss.qualcomm.com>
On 9/18/2025 3:57 PM, Konrad Dybcio wrote:
> On 9/18/25 11:40 AM, Md Sadre Alam wrote:
>> BAM version 1.6.0 and later changed the behavior of the mask field in
>> command elements for read operations. In newer BAM versions, the mask
>> field for read commands contains the upper 4 bits of the destination
>> address to support 36-bit addressing, while for write commands it
>> continues to function as a traditional write mask.
>
> So the hardware can read from higher addresses but not write to them?
No,
Write Operations: Can target any 32-bit address in the peripheral
address space (up to 4GB)
Read Operations: Can read from any 32-bit peripheral address and
place the data into 36-bit memory addresses (up to 64GB) starting
from BAM v1.6.0
>
> Plus, you didn't explain what the mask register does on BAM <1.6.0.
> If it really masks the address, all reads will now point to 0x0
The mask field never masks addresses in any BAM version. Here's the
complete specification:
BAM Command Element Structure
Write Command Elements (All BAM Versions):
| Field | Bits | Description |
|--------|-------|-----------------------------------------------------|
| 1st DW | 31:24 | Command (must be 0 for write) |
| | 23:0 | Address - target address in peripheral |
|-----------------------------------------------------------------------
| 2nd DW | 31:0 | Data - the data to be written |
------------------------------------------------------------------------
| 3rd DW | 31:0 | Mask - 32-bit mask defining which bits to modify |
-----------------------------------------------------------------------
| 4th DW | 31:0 | Reserved |
------------------------------------------------------------------------
Read Command Elements (BAM < v1.6.0):
| Field | Bits | Description |
|--------|-------|-----------------------------------------------------|
| 1st DW | 31:24 | Command (must be 1 for read) |
| | 23:0 | Address - source address in peripheral |
------------------------------------------------------------------------
| 2nd DW | 31:0 | Destination - memory address to write read-data |
------------------------------------------------------------------------
| 3rd DW | 31:0 | Reserved (IGNORED by hardware) |
------------------------------------------------------------------------
| 4th DW | 31:0 | Reserved |
------------------------------------------------------------------------
Read Command Elements (BAM >= v1.6.0):
| Field | Bits | Description |
|--------|-------|-----------------------------------------------------|
| 1st DW | 31:24 | Command (must be 1 for read) |
| | 23:0 | Address - source address in peripheral |
------------------------------------------------------------------------
| 2nd DW | 31:0 | Destination - 32 LSBs of 36-bit destination addr |
------------------------------------------------------------------------
| 3rd DW | 31:4 | Reserved |
| | 3:0 | Destination Address 4 MSBs (bits 35:32) |
------------------------------------------------------------------------
| 4th DW | 31:0 | Reserved |
------------------------------------------------------------------------
For Read Commands:
- BAM < v1.6.0: 3rd Dword completely ignored by hardware
- BAM >= v1.6.0: 3rd Dword[3:0] contains upper 4 bits of destination
address
Thanks,
Alam.
next prev parent reply other threads:[~2025-09-19 5:57 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-18 9:40 [PATCH 0/9] Add QPIC SPI NAND support for IPQ5424 and IPQ5332 platforms Md Sadre Alam
2025-09-18 9:40 ` [PATCH 1/9] spi: dt-bindings: spi-qpic-snand: Add IPQ5424 compatible Md Sadre Alam
2025-09-22 17:28 ` Rob Herring (Arm)
2025-09-18 9:40 ` [PATCH 2/9] spi: dt-bindings: spi-qpic-snand: Add IPQ5332 compatible Md Sadre Alam
2025-09-22 17:28 ` Rob Herring (Arm)
2025-09-18 9:40 ` [PATCH 3/9] dma: qcom: bam_dma: Fix command element mask field for BAM v1.6.0+ Md Sadre Alam
2025-09-18 10:27 ` Konrad Dybcio
2025-09-19 5:56 ` Md Sadre Alam [this message]
2025-09-24 5:16 ` Lakshmi Sowjanya D (QUIC)
2025-10-08 11:35 ` Konrad Dybcio
2025-09-18 9:40 ` [PATCH 4/9] arm64: dts: qcom: ipq5424: Add QPIC SPI NAND controller support Md Sadre Alam
2025-09-18 9:40 ` [PATCH 5/9] arm64: dts: qcom: ipq5332: " Md Sadre Alam
2025-09-18 9:40 ` [PATCH 6/9] arm64: dts: qcom: ipq5424: Enable QPIC SPI NAND support Md Sadre Alam
2025-09-18 12:48 ` Konrad Dybcio
2025-09-19 6:00 ` Md Sadre Alam
2025-09-18 9:40 ` [PATCH 7/9] arm64: dts: qcom: ipq5332: " Md Sadre Alam
2025-09-18 12:49 ` Konrad Dybcio
2025-09-18 9:40 ` [PATCH 8/9] arm64: dts: qcom: ipq5424: Remove eMMC support Md Sadre Alam
2025-09-18 12:46 ` Konrad Dybcio
2025-09-18 12:49 ` Konrad Dybcio
2025-09-19 5:58 ` Md Sadre Alam
2025-09-18 9:40 ` [PATCH 9/9] arm64: dts: qcom: ipq5332: " Md Sadre Alam
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