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([2401:4900:1c5f:7a7d:9c44:b2ee:ae34:5374]) by smtp.gmail.com with ESMTPSA id o11-20020a17090a744b00b002311f887aeasm1992634pjk.1.2023.02.09.00.25.46 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 09 Feb 2023 00:25:50 -0800 (PST) Message-ID: <32153a4b-9974-a42a-ef30-c0bd8cbc732b@linaro.org> Date: Thu, 9 Feb 2023 13:55:44 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.3.1 Subject: Re: [PATCH] dt-bindings: dma: qcom,bam-dma: add optional memory interconnect properties Content-Language: en-US To: neil.armstrong@linaro.org, Krzysztof Kozlowski , Dmitry Baryshkov , Andy Gross , Bjorn Andersson , Konrad Dybcio , Vinod Koul , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20230207-topic-sm8550-upstream-bam-dma-bindings-fix-v1-1-57dba71e8727@linaro.org> <88c31e71-55b6-a20d-1fcf-07804eace54b@linaro.org> <0f16d63f-3bb0-54aa-bcb4-4c666d4b2846@linaro.org> From: Bhupesh Sharma In-Reply-To: <0f16d63f-3bb0-54aa-bcb4-4c666d4b2846@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org On 2/8/23 2:38 PM, neil.armstrong@linaro.org wrote: > On 08/02/2023 10:03, Krzysztof Kozlowski wrote: >> On 07/02/2023 16:27, Dmitry Baryshkov wrote: >>> On 07/02/2023 15:35, Neil Armstrong wrote: >>>> On 07/02/2023 11:32, Dmitry Baryshkov wrote: >>>>> On 07/02/2023 12:03, Neil Armstrong wrote: >>>>>> Recents SoCs like the SM8450 or SM8550 requires memory interconnect >>>>>> in order to have functional DMA. >>>>>> >>>>>> Signed-off-by: Neil Armstrong >>>>>> --- >>>>>>    Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml | 6 ++++++ >>>>>>    1 file changed, 6 insertions(+) >>>>> >>>>> I suspect this will not work without a change for a driver. >>>>> >>>> >>>> I had the impression single interconnect entries would be taken in >>>> account >>>> by the platform core, but it doesn't seem to be the case, anyway I >>>> can;t >>>> find >>>> any code doing that. >>> >>> Probably you mixed interconnects and power-domains here. >>> >> >> The driver change was submitted some time ago: >> https://lore.kernel.org/all/20210505213731.538612-10-bhupesh.sharma@linaro.org/ >> >> There is already DTS user of it and we expect driver to be resubmitted >> at some point. >> >> What I don't really get is that crypto driver sets bandwidth for >> interconnects, not the BAM. Why BAM needs interconnect? Usually you do >> not need to initialize some middle paths. Getting the final interconnect >> path (e.g. crypto-memory) is enough, because it includes everything in >> between. > > Indeed the interconnect on BAM may be redundant since QCE sets the BW, > I'll investigate to understand if it's also necessary on BAM. Since we are already doing this via QCE driver (since crypto block on qcom SoCs employs BAM DMA services) via [1], this change is not needed for sm8150, sm8250, sm8350 and subsequent qcom SoCs (available presently), so this patch can be dropped. [1]. https://www.spinics.net/lists/linux-arm-msm/msg142957.html Thanks, Bhupesh