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Tue, 28 Nov 2023 16:44:36 -0600 Received: from [172.19.74.144] (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2507.34 via Frontend Transport; Tue, 28 Nov 2023 16:44:35 -0600 Message-ID: <3403ac76-db69-d2c2-0bd1-03e8210d309e@amd.com> Date: Tue, 28 Nov 2023 14:44:35 -0800 Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.11.0 Subject: Re: [PATCH 1/3] dmaengine: xilinx: xdma: Fix the count of elapsed periods in cyclic mode Content-Language: en-US To: Miquel Raynal , Vinod Koul , Brian Xu , Raj Kumar Rampelli , CC: Michal Simek , Thomas Petazzoni References: <20231124150923.257687-1-miquel.raynal@bootlin.com> <20231124150923.257687-2-miquel.raynal@bootlin.com> From: Lizhi Hou In-Reply-To: <20231124150923.257687-2-miquel.raynal@bootlin.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044FD:EE_|BL1PR12MB5352:EE_ X-MS-Office365-Filtering-Correlation-Id: a19920cc-4315-4b02-fc16-08dbf0639939 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Nov 2023 22:44:36.4793 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a19920cc-4315-4b02-fc16-08dbf0639939 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044FD.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5352 On 11/24/23 07:09, Miquel Raynal wrote: > Xilinx DMA engine is capable of keeping track of the number of elapsed > periods and this is an increasing 32-bit counter which is only reset > when turning off the engine. No need to add this value to our local > counter. > > Fixes: cd8c732ce1a5 ("dmaengine: xilinx: xdma: Support cyclic transfers") > Signed-off-by: Miquel Raynal > --- > > Hello, so far all my testing was performed by looping the playback > output to the recording input and comparing the files using > FFTs. Unfortunately, when the DMA engine suffers from the same issue on > both sides, some issues may appear un-noticed, which is likely what > happened here as the tooling did not report any issue while analyzing > the output until I actually listened to real audio now that I have in my > hands the relevant hardware/connectors to do so. > --- > drivers/dma/xilinx/xdma.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/dma/xilinx/xdma.c b/drivers/dma/xilinx/xdma.c > index 84a88029226f..75533e787414 100644 > --- a/drivers/dma/xilinx/xdma.c > +++ b/drivers/dma/xilinx/xdma.c > @@ -754,7 +754,7 @@ static irqreturn_t xdma_channel_isr(int irq, void *dev_id) > if (ret) > goto out; > > - desc->completed_desc_num += complete_desc_num; > + desc->completed_desc_num = complete_desc_num; Based on PG195, completed descriptor count will be reset to 0 on rising edge of Control register Run bit. That means it resets to zero for each transaction. This change breaks our long sg list test. Lizhi > > if (desc->cyclic) { > ret = regmap_read(xdev->rmap, xchan->base + XDMA_CHAN_STATUS,