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Wed, 22 Apr 2026 23:38:47 -0700 (PDT) X-Received: by 2002:a17:90b:2244:b0:35e:57cf:c0a3 with SMTP id 98e67ed59e1d1-361404a6b1bmr26676545a91.26.1776926327109; Wed, 22 Apr 2026 23:38:47 -0700 (PDT) Received: from [10.217.219.207] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-361410a7ab7sm24264844a91.10.2026.04.22.23.38.40 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 22 Apr 2026 23:38:46 -0700 (PDT) Message-ID: <3b99fdf3-3822-4c75-84a9-2371bea24beb@oss.qualcomm.com> Date: Thu, 23 Apr 2026 12:08:39 +0530 Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 4/4] i2c: qcom-geni: Support multi-owner controllers in GPI mode To: Konrad Dybcio , Mukesh Kumar Savaliya , viken.dadhaniya@oss.qualcomm.com, andi.shyti@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, vkoul@kernel.org, Frank.Li@kernel.org, andersson@kernel.org, konradybcio@kernel.org, dmitry.baryshkov@oss.qualcomm.com, linmq006@gmail.com, quic_jseerapu@quicinc.com, agross@kernel.org, linux-arm-msm@vger.kernel.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org Cc: krzysztof.kozlowski@oss.qualcomm.com, bartosz.golaszewski@oss.qualcomm.com, bjorn.andersson@oss.qualcomm.com References: <20260331114742.2896317-1-mukesh.savaliya@oss.qualcomm.com> <20260331114742.2896317-5-mukesh.savaliya@oss.qualcomm.com> <52685536-6b77-497b-aa48-621a82da2a0e@oss.qualcomm.com> Content-Language: en-US From: Mukesh Savaliya In-Reply-To: <52685536-6b77-497b-aa48-621a82da2a0e@oss.qualcomm.com> Content-Type: text/plain; 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On 4/1/2026 3:51 PM, Konrad Dybcio wrote: > On 3/31/26 1:47 PM, Mukesh Kumar Savaliya wrote: >> Some platforms use a QUP-based I2C controller in a configuration where the >> controller is shared with another system processor. In this setup the >> operating system must not assume exclusive ownership of the controller or >> its associated pins. >> >> Add support for enabling multi-owner operation when DeviceTree specifies >> qcom,qup-multi-owner. When enabled, mark the underlying serial engine as >> shared so the common GENI resource handling avoids selecting the "sleep" >> pinctrl state, which could disrupt transfers initiated by the other >> processor. >> >> For GPI mode transfers, request lock/unlock TRE sequencing from the GPI >> driver by setting a single lock_action selector per message, emitting lock >> before the first message and unlock after the last message (handling the >> single-message case as well). This serializes access to the shared >> controller without requiring message-position flags to be passed into the >> DMA engine layer. >> >> Signed-off-by: Mukesh Kumar Savaliya >> --- > > [...] > >> + if (of_property_read_bool(pdev->dev.of_node, "qcom,qup-multi-owner")) { >> + /* >> + * Multi-owner controller configuration: the controller may be >> + * used by another system processor. Mark the SE as shared so >> + * common GENI resource handling can avoid pin state changes >> + * that would disrupt the other user. >> + */ > > I don't find this comment very useful given we have kerneldoc for that > property and the behavior you described impacts another file > Makes sense, will remove this comment in the next patch upload. > [...] > >> + if (gi2c->se.multi_owner) >> + dev_err_probe(dev, -EINVAL, "I2C sharing not supported in non GSI mode\n"); > > return dev_err_probe() > Done, Thanks ! > Konrad >