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Wed, 04 Sep 2024 18:21:41 +0000 (GMT) Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 484ILeKK026328 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 4 Sep 2024 18:21:40 GMT Received: from [10.216.2.237] (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 4 Sep 2024 11:21:37 -0700 Message-ID: <46653560-d8ea-4255-9df2-40a141d16fe3@quicinc.com> Date: Wed, 4 Sep 2024 23:51:32 +0530 Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 0/4] Enable shared SE support over I2C To: Bryan O'Donoghue , , , , , , , CC: References: <20240829092418.2863659-1-quic_msavaliy@quicinc.com> <9eed39f3-baf3-41cb-bd19-361d76207b09@linaro.org> Content-Language: en-US From: Mukesh Kumar Savaliya In-Reply-To: <9eed39f3-baf3-41cb-bd19-361d76207b09@linaro.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: dI7adEftBAyJ8zeSt_UJfxJmbXNDVk-8 X-Proofpoint-GUID: dI7adEftBAyJ8zeSt_UJfxJmbXNDVk-8 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-04_16,2024-09-04_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=1 adultscore=0 impostorscore=0 clxscore=1015 priorityscore=1501 suspectscore=0 phishscore=0 lowpriorityscore=0 mlxscore=1 mlxlogscore=191 spamscore=1 malwarescore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2409040138 On 8/29/2024 3:26 PM, Bryan O'Donoghue wrote: > On 29/08/2024 10:24, Mukesh Kumar Savaliya wrote: >> This Series adds support to share QUP based I2C SE between subsystems. >> Each subsystem should have its own GPII which interacts between SE and >> GSI DMA HW engine. > > What is SE ? > > GPII - general purpose interrupt ... ? > > You have too many acronyms here, which makes reading and understanding > your cover letter a bit hard. > > Please define at least the term SE in your cover letter and in your patch. > > In the patch you use the term TRE which without diving into the code I > vaguely remember is a register.. > > - GPII > - GSI > - SE > - TRE > > Need to be defined to make what's going on in this series more "grokable". > > A cover letter should assume a reviewer is familiar with the basics of a > system - no need to define what I2C is but, similarly shouldn't assume a > reviewer is numerate in the taxonomy of vendor specific architecture > e.g. whats SE ? > > --- Sure, Understood what to mention instead of short names. Let me have cover letter and upload next patch. > bod