From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Subject: [v1] dmaengine: tegra: Use relaxed versions of readl/writel From: Dmitry Osipenko Message-Id: <49392c02-6dcc-9a95-0035-27c4c0d14820@gmail.com> Date: Fri, 26 Apr 2019 15:18:40 +0300 To: Jon Hunter , Laxman Dewangan , Vinod Koul , Thierry Reding Cc: dmaengine@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org List-ID: MjYuMDQuMjAxOSAxNDoxMywgSm9uIEh1bnRlciDQv9C40YjQtdGCOgo+IAo+IE9uIDI2LzA0LzIw MTkgMTE6NDUsIERtaXRyeSBPc2lwZW5rbyB3cm90ZToKPj4gMjYuMDQuMjAxOSAxMjo1MiwgSm9u IEh1bnRlciDQv9C40YjQtdGCOgo+Pj4KPj4+IE9uIDI1LzA0LzIwMTkgMDA6MTcsIERtaXRyeSBP c2lwZW5rbyB3cm90ZToKPj4+PiBUaGUgcmVhZGwvd3JpdGVsIGZ1bmN0aW9ucyBhcmUgaW5zZXJ0 aW5nIG1lbW9yeSBiYXJyaWVyIGluIG9yZGVyIHRvCj4+Pj4gZW5zdXJlIHRoYXQgbWVtb3J5IHN0 b3JlcyBhcmUgY29tcGxldGVkLiBPbiBUZWdyYTIwIGFuZCBUZWdyYTMwIHRoaXMKPj4+PiByZXN1 bHRzIGluIEwyIGNhY2hlIHN5bmNpbmcgd2hpY2ggaXNuJ3QgYSBjaGVhcGVzdCBvcGVyYXRpb24u IFRoZQo+Pj4+IHRlZ3JhMjAtYXBiLWRtYSBkcml2ZXIgZG9lc24ndCBuZWVkIHRvIHN5bmNocm9u aXplIGdlbmVyaWMgbWVtb3J5Cj4+Pj4gYWNjZXNzZXMsIGhlbmNlIHVzZSB0aGUgcmVsYXhlZCB2 ZXJzaW9ucyBvZiB0aGUgZnVuY3Rpb25zLgo+Pj4KPj4+IERvIHlvdSBtZWFuIGRldmljZS1pbyBh Y2Nlc3NlcyBoZXJlIGFzIHRoaXMgaXMgbm90IGdlbmVyaWMgbWVtb3J5Pwo+Pgo+PiBZZXMuIFRo ZSBJT01FTSBhY2Nlc3NlcyB3aXRoaW4gYXJlIGFsd2F5cyBvcmRlcmVkIGFuZCB1bmNhY2hlZCwg d2hpbGUKPj4gZ2VuZXJpYyBtZW1vcnkgYWNjZXNzZXMgYXJlIG91dC1vZi1vcmRlciBhbmQgY2Fj aGVkLgo+Pgo+Pj4gQWx0aG91Z2ggdGhlcmUgbWF5IG5vdCBiZSBhbnkgaXNzdWVzIHdpdGggdGhp cyBjaGFuZ2UsIEkgdGhpbmsgSSBuZWVkIGEKPj4+IGJpdCBtb3JlIGNvbnZpbmNpbmcgdGhhdCB3 ZSBzaG91bGQgZG8gdGhpcyBnaXZlbiB0aGF0IHdlIGhhdmUgaGFkIGl0Cj4+PiB0aGlzIHdheSBm b3Igc29tZXRpbWUgYW5kIEkgd291bGQgbm90IGxpa2UgdG8gc2VlIHVzIGludHJvZHVjZSBhbnkK Pj4+IHJlZ3Jlc3Npb25zIGFzIHRoaXMgcG9pbnQgd2l0aG91dCBiZWluZyAxMDAlIGNlcnRhaW4g d2Ugd291bGQgbm90Lgo+Pj4gSWRlYWxseSwgaWYgSSBoYWQgc29tZSBnb29kIGV4dGVuc2l2ZSB0 ZXN0cyBJIGNvdWxkIHJ1biB0byBoYW1tZXIgdGhlCj4+PiBETUEgZm9yIGFsbCBjb25maWd1cmF0 aW9ucyB3aXRoIGRpZmZlcmVudCBjb21iaW5hdGlvbnMgb2YgY2hhbm5lbHMKPj4+IHJ1bm5pbmcg c2ltdWx0YW5lb3VzbHkgdGhlbiB3ZSBjb3VsZCB0ZXN0IHRoaXMsIGJ1dCByaWdodCBub3cgSSBk b24ndCA6LSgKPj4+Cj4+PiBIYXZlIHlvdSAuLi4KPj4+IDEuIFRlc3RlZCBib3RoIGN5Y2xpYyBh bmQgc2NhdHRlci1nYXRoZXIgdHJhbnNmZXJzPwo+Pj4gMi4gU3RyZXNzIHRlc3RlZCBzaW11bHRh bmVvdXMgdHJhbnNmZXJzIHdpdGggdmFyaW91cyBkaWZmZXJlbnQKPj4+ICAgIGNvbmZpZ3VyYXRp b25zPwo+Pj4gMy4gUXVhbnRpZmllZCB0aGUgYWN0dWFsIHBlcmZvcm1hbmNlIGJlbmVmaXQgb2Yg dGhpcyBjaGFuZ2Ugc28gd2UgY2FuCj4+PiAgICB1bmRlcnN0YW5kIGhvdyBtdWNoIG9mIGEgcGVy Zm9ybWFuY2UgYm9vc3QgdGhpcyBvZmZlcnM/Cj4+Cj4+IEFjdHVhbGx5IEkgZm91bmQgYSBjYXNl IHdoZXJlIHRoaXMgY2hhbmdlIGNhdXNlcyBhIHByb2JsZW0sIEknbSBzZWVpbmcKPj4gSTJDIHRy YW5zZmVyIHRpbWVvdXQgZm9yIHRvdWNoc2NyZWVuIGFuZCBpdCBicmVha3MgdGhlIHRvdWNoIGlu cHV0Lgo+PiBJbmRlZWQsIEkgaGF2ZW4ndCB0ZXN0ZWQgdGhpcyBwYXRjaCB2ZXJ5IHdlbGwuCj4+ Cj4+IEFuZCB0aGUgZml4IGlzIHRoaXM6Cj4+Cj4+IEBAIC0xNTkyLDYgKzE1OTIsOCBAQCBzdGF0 aWMgaW50IHRlZ3JhX2RtYV9ydW50aW1lX3N1c3BlbmQoc3RydWN0IGRldmljZQo+PiAqZGV2KQo+ PiAgCQkJCQkJICBURUdSQV9BUEJETUFfQ0hBTl9XQ09VTlQpOwo+PiAgCX0KPj4KPj4gKwlkc2Io KTsKPj4gKwo+PiAgCWNsa19kaXNhYmxlX3VucHJlcGFyZSh0ZG1hLT5kbWFfY2xrKTsKPj4KPj4g IAlyZXR1cm4gMDsKPj4KPj4KPj4gQXBwYXJlbnRseSB0aGUgcHJvYmxlbSBpcyB0aGF0IENMSy9E TUEgKFBQU0IvQVBCKSBhY2Nlc3NlcyBhcmUKPj4gaW5jb2hlcmVudCBhbmQgQ1BVIGRpc2FibGVz IGNsb2NrIGJlZm9yZSB3cml0ZXMgYXJlIHJlYWNoaW5nIERNQSBjb250cm9sbGVyLgo+Pgo+PiBJ J2Qgc2F5IHRoYXQgY3ljbGljIGFuZCBzY2F0dGVyLWdhdGhlciB0cmFuc2ZlcnMgYXJlIG5vdyB0 ZXN0ZWQuIEkgYWxzbwo+PiBtYWRlIHNvbWUgbW9yZSB0ZXN0aW5nIG9mIHNpbXVsdGFuZW91cyB0 cmFuc2ZlcnMuCj4+Cj4+IFF1YW50aWZ5aW5nIHBlcmZvcm1hbmNlIHByb2JhYmx5IHdvbid0IGJl IGVhc3kgdG8gbWFrZSBhcyB0aGUgRE1BCj4+IHJlYWQvd3JpdGVzIGFyZSBub3Qgb24gYW55IGtp bmQgb2YgY29kZSdzIGhvdC1wYXRoLgo+IAo+IFNvIHdoeSBtYWtlIHRoZSBjaGFuZ2U/CgpGb3Ig Y29uc2lzdGVuY3kuCgo+PiBKb24sIGFyZSB5b3Ugc3RpbGwgaW5zaXN0aW5nIGFib3V0IHRvIGRy b3AgdGhpcyBwYXRjaCBvciB5b3Ugd2lsbCBiZQo+PiBmaW5lIHdpdGggdGhlIHYyIHRoYXQgd2ls bCBoYXZlIHRoZSBkc2IoKSBpbiBwbGFjZT8KPiAKPiBJZiB3ZSBjYW4ndCBxdWFudGlmeSB0aGUg cGVyZm9ybWFuY2UgZ2FpbiwgdGhlbiBpdCBpcyBkaWZmaWN1bHQgdG8KPiBqdXN0aWZ5IHRoZSBj aGFuZ2UuIEkgd291bGQgYWxzbyBiZSBjb25jZXJuZWQgaWYgdGhhdCBpcyB0aGUgb25seSBwbGFj ZQo+IHdlIG5lZWQgYW4gZXhwbGljaXQgZHNiLgoKTWF5YmUgaXQgd29uJ3QgaHVydCB0byBhZGQg ZHNiIHRvIHRoZSBJU1IgYXMgd2VsbC4gQnV0IG9rYXksIGxldCdzIGRyb3AKdGhpcyBwYXRjaCBm b3Igbm93Lgo= From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 289EFC43218 for ; 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[94.29.35.107]) by smtp.googlemail.com with ESMTPSA id e14sm6182163ljk.45.2019.04.26.05.18.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 26 Apr 2019 05:18:41 -0700 (PDT) Subject: Re: [PATCH v1] dmaengine: tegra: Use relaxed versions of readl/writel To: Jon Hunter , Laxman Dewangan , Vinod Koul , Thierry Reding Cc: dmaengine@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org References: <20190424231708.21219-1-digetx@gmail.com> <4a315b63-bc71-3c3e-f1ae-8638bcf4033d@gmail.com> From: Dmitry Osipenko Message-ID: <49392c02-6dcc-9a95-0035-27c4c0d14820@gmail.com> Date: Fri, 26 Apr 2019 15:18:40 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.6.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="UTF-8" Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org Message-ID: <20190426121840._gsftLAQrSYKuXcI50lMjI-kE8lzoatSv-08KbN0Hio@z> 26.04.2019 14:13, Jon Hunter пишет: > > On 26/04/2019 11:45, Dmitry Osipenko wrote: >> 26.04.2019 12:52, Jon Hunter пишет: >>> >>> On 25/04/2019 00:17, Dmitry Osipenko wrote: >>>> The readl/writel functions are inserting memory barrier in order to >>>> ensure that memory stores are completed. On Tegra20 and Tegra30 this >>>> results in L2 cache syncing which isn't a cheapest operation. The >>>> tegra20-apb-dma driver doesn't need to synchronize generic memory >>>> accesses, hence use the relaxed versions of the functions. >>> >>> Do you mean device-io accesses here as this is not generic memory? >> >> Yes. The IOMEM accesses within are always ordered and uncached, while >> generic memory accesses are out-of-order and cached. >> >>> Although there may not be any issues with this change, I think I need a >>> bit more convincing that we should do this given that we have had it >>> this way for sometime and I would not like to see us introduce any >>> regressions as this point without being 100% certain we would not. >>> Ideally, if I had some good extensive tests I could run to hammer the >>> DMA for all configurations with different combinations of channels >>> running simultaneously then we could test this, but right now I don't :-( >>> >>> Have you ... >>> 1. Tested both cyclic and scatter-gather transfers? >>> 2. Stress tested simultaneous transfers with various different >>> configurations? >>> 3. Quantified the actual performance benefit of this change so we can >>> understand how much of a performance boost this offers? >> >> Actually I found a case where this change causes a problem, I'm seeing >> I2C transfer timeout for touchscreen and it breaks the touch input. >> Indeed, I haven't tested this patch very well. >> >> And the fix is this: >> >> @@ -1592,6 +1592,8 @@ static int tegra_dma_runtime_suspend(struct device >> *dev) >> TEGRA_APBDMA_CHAN_WCOUNT); >> } >> >> + dsb(); >> + >> clk_disable_unprepare(tdma->dma_clk); >> >> return 0; >> >> >> Apparently the problem is that CLK/DMA (PPSB/APB) accesses are >> incoherent and CPU disables clock before writes are reaching DMA controller. >> >> I'd say that cyclic and scatter-gather transfers are now tested. I also >> made some more testing of simultaneous transfers. >> >> Quantifying performance probably won't be easy to make as the DMA >> read/writes are not on any kind of code's hot-path. > > So why make the change? For consistency. >> Jon, are you still insisting about to drop this patch or you will be >> fine with the v2 that will have the dsb() in place? > > If we can't quantify the performance gain, then it is difficult to > justify the change. I would also be concerned if that is the only place > we need an explicit dsb. Maybe it won't hurt to add dsb to the ISR as well. But okay, let's drop this patch for now.