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Wed, 04 Sep 2024 18:23:53 +0000 (GMT) Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 484INqTv009548 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 4 Sep 2024 18:23:52 GMT Received: from [10.216.2.237] (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 4 Sep 2024 11:23:49 -0700 Message-ID: <523acc68-2e85-4e33-b87f-8400411ac00b@quicinc.com> Date: Wed, 4 Sep 2024 23:53:45 +0530 Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 2/4] dma: gpi: Add Lock and Unlock TRE support to access SE exclusively To: Bryan O'Donoghue , , , , , , , CC: References: <20240829092418.2863659-1-quic_msavaliy@quicinc.com> <20240829092418.2863659-3-quic_msavaliy@quicinc.com> <0712caf4-568f-4c7c-b319-ccdbba37142a@linaro.org> Content-Language: en-US From: Mukesh Kumar Savaliya In-Reply-To: <0712caf4-568f-4c7c-b319-ccdbba37142a@linaro.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: wkyLMmrLeItekqGCmiELtRq4uVhtUgPB X-Proofpoint-ORIG-GUID: wkyLMmrLeItekqGCmiELtRq4uVhtUgPB X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-04_16,2024-09-04_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 mlxscore=0 suspectscore=0 lowpriorityscore=0 mlxlogscore=999 priorityscore=1501 spamscore=0 malwarescore=0 adultscore=0 bulkscore=0 impostorscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2409040138 On 8/29/2024 3:35 PM, Bryan O'Donoghue wrote: > On 29/08/2024 10:24, Mukesh Kumar Savaliya wrote: >> GSI DMA provides specific TREs namely Lock and Unlock TRE, which >> provides mutual exclusive access to SE from any of the subsystem >> (E.g. Apps, TZ, ADSP etc). Lock prevents other subsystems from >> concurrently performing DMA transfers and avoids disturbance to >> data path. Basically lock the SE for particular subsystem, complete >> the transfer, unlock the SE. >> >> Apply Lock TRE for the first transfer of shared SE and Apply Unlock >> TRE for the last transfer. >> >> Also change MAX_TRE macro to 5 from 3 because of the two additional TREs. >> >> Signed-off-by: Mukesh Kumar Savaliya >> --- >>   drivers/dma/qcom/gpi.c           | 37 +++++++++++++++++++++++++++++++- >>   include/linux/dma/qcom-gpi-dma.h |  6 ++++++ >>   2 files changed, 42 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/dma/qcom/gpi.c b/drivers/dma/qcom/gpi.c >> index e6ebd688d746..ba11b2641ab6 100644 >> --- a/drivers/dma/qcom/gpi.c >> +++ b/drivers/dma/qcom/gpi.c >> @@ -2,6 +2,7 @@ >>   /* >>    * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. >>    * Copyright (c) 2020, Linaro Limited >> + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights >> reserved. >>    */ >>   #include >> @@ -65,6 +66,14 @@ >>   /* DMA TRE */ >>   #define TRE_DMA_LEN        GENMASK(23, 0) >> +/* Lock TRE */ >> +#define TRE_I2C_LOCK        BIT(0) >> +#define TRE_MINOR_TYPE        GENMASK(19, 16) >> +#define TRE_MAJOR_TYPE        GENMASK(23, 20) >> + >> +/* Unlock TRE */ >> +#define TRE_I2C_UNLOCK        BIT(8) >> + >>   /* Register offsets from gpi-top */ >>   #define GPII_n_CH_k_CNTXT_0_OFFS(n, k)    (0x20000 + (0x4000 * (n)) >> + (0x80 * (k))) >>   #define GPII_n_CH_k_CNTXT_0_EL_SIZE    GENMASK(31, 24) >> @@ -516,7 +525,7 @@ struct gpii { >>       bool ieob_set; >>   }; >> -#define MAX_TRE 3 >> +#define MAX_TRE 5 >>   struct gpi_desc { >>       struct virt_dma_desc vd; >> @@ -1637,6 +1646,19 @@ static int gpi_create_i2c_tre(struct gchan >> *chan, struct gpi_desc *desc, >>       struct gpi_tre *tre; >>       unsigned int i; >> +    /* create lock tre for first tranfser */ >> +    if (i2c->shared_se && i2c->first_msg) { >> +        tre = &desc->tre[tre_idx]; >> +        tre_idx++; >> + >> +        tre->dword[0] = 0; >> +        tre->dword[1] = 0; >> +        tre->dword[2] = 0; >> +        tre->dword[3] = u32_encode_bits(1, TRE_I2C_LOCK); >> +        tre->dword[3] |= u32_encode_bits(0, TRE_MINOR_TYPE); >> +        tre->dword[3] |= u32_encode_bits(3, TRE_MAJOR_TYPE); >> +    } >> + >>       /* first create config tre if applicable */ >>       if (i2c->set_config) { >>           tre = &desc->tre[tre_idx]; >> @@ -1695,6 +1717,19 @@ static int gpi_create_i2c_tre(struct gchan >> *chan, struct gpi_desc *desc, >>           tre->dword[3] |= u32_encode_bits(1, TRE_FLAGS_IEOT); >>       } >> +    /* Unlock tre for last transfer */ >> +    if (i2c->shared_se && i2c->last_msg && i2c->op != I2C_READ) { >> +        tre = &desc->tre[tre_idx]; >> +        tre_idx++; >> + >> +        tre->dword[0] = 0; >> +        tre->dword[1] = 0; >> +        tre->dword[2] = 0; >> +        tre->dword[3] = u32_encode_bits(1, TRE_I2C_UNLOCK); >> +        tre->dword[3] |= u32_encode_bits(1, TRE_MINOR_TYPE); >> +        tre->dword[3] |= u32_encode_bits(3, TRE_MAJOR_TYPE); >> +    } >> + > > What happens if the first transfer succeeds => bus lock but the last > transfer fails => !unlock ? > > Is the SE left in a locked state ? > Here, it's GSI running the transfer descriptors and if it fails, we do dmaengine_terminate_sync() at i2c client side. It clears the descriptors and unmaps the buffer. SE remains in unlocked like initial state. > --- > bod