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Tue, 27 Sep 2022 12:18:55 -0500 Message-ID: <5f77987e-49bc-e035-19e0-52c25f4adc7e@amd.com> Date: Tue, 27 Sep 2022 10:18:54 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.11.0 Subject: Re: [PATCH V4 XDMA 2/2] dmaengine: xilinx: xdma: Add user logic interrupt support Content-Language: en-US To: =?UTF-8?Q?Martin_T=c5=afma?= , , , , CC: , , , References: <1663871905-60498-1-git-send-email-lizhi.hou@amd.com> <1663871905-60498-3-git-send-email-lizhi.hou@amd.com> <64388266-1707-ee20-c3ab-edb67ada68dc@amd.com> From: Lizhi Hou In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT081:EE_|SN7PR12MB6692:EE_ X-MS-Office365-Filtering-Correlation-Id: 0d0a9180-cad9-4413-b1ba-08daa0ac5c6a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: ZVnGIhznrSF1MwFFYtMU7YvopMgzxY4a8zaGa8QSYvjelhLHtQbgNQqK6Hu1TRyYIz5+4SxzicuL2PSdfvLdHFRjfUSeLM0OKlB9EtjrnVAHeuLDCjq3rpsMVWuah7+P4JBfrXeAM1UMfo781d6neFRwj3x5cSd2Pg4kY/dXoZMezEeZ7r5ieRfYTOFbRRo4O+lCp6Bgki7rvEg+tn7doM9C+MAG/ai1f/9OMKgL0IuqxR98m1EMPREj/pJs4CNP/q89grM9Qy5YZYGJ8okcM7ePV+SRjLXcus4rssHWUc7ADtP8z07vUm3z/p1gyuH6A7LFaHKG0tU7k2B7d0WnSaYfCGOAuwfn5OLxQdACpFH4jM4RlGdtil8iUjG8ea8S1morW6+8a4MNS6VOm7qqU0NgQL0h1vqc4skcnBKbMIBEbM6An/XNSDmBchq3U2G9PAUcgPQicU6Kwy63cY0Q5CsQCVLhNuB3A8ke0/ZtlqtPFzo0/G83qlqd4b35LPDrBJddFyXMNwoq/lOJS97Cf/0BRaMlhza+QobhIyvAe0ncqdgVqSsPZIEpd6lyNqbRyO21d0tR6dsUDBl5EZzqvzNwZV/pPsxv8yOuYGgfsPpfonFhVGgpnprBtzcH61Xh/8kTKNCEx4XmaZDXPC1ddgrKCPPzxY2mFm6W9GR+TGk+NrkVOoEA4Ojemy92TqrEBMfEbvUobKLASE6NY1ICRKYCCB4t5pbtphHb9cf+BscXGrUtUvtVrKLH1neHGJgKlQSJb4YhiBjPmZPLfhmObBNKsK31Dl1As9ic/7/xSpfGTQ8djcQZ68gqB6UxYuZxlYKtfGgrunpMtso2TteMyg== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(39860400002)(376002)(136003)(396003)(346002)(451199015)(40470700004)(46966006)(36840700001)(2906002)(36860700001)(82740400003)(426003)(70206006)(8936002)(70586007)(83380400001)(16576012)(41300700001)(82310400005)(478600001)(5660300002)(26005)(36756003)(44832011)(40480700001)(186003)(356005)(336012)(110136005)(66574015)(54906003)(31686004)(86362001)(2616005)(81166007)(53546011)(8676002)(4326008)(316002)(40460700003)(31696002)(47076005)(43740500002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Sep 2022 17:18:56.9161 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0d0a9180-cad9-4413-b1ba-08daa0ac5c6a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT081.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB6692 Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org On 9/27/22 09:46, Martin Tůma wrote: > On 27. 09. 22 18:28, Lizhi Hou wrote: > >> Okay, I got the point. How about changing request/remove APIs to >> enable/disable APIs as below >> >>       xdma_enable_user_irq(struct platform_device *pdev, u32 >> user_irq_index, u32 *irq) >> >>              user_irq_index: user logic interrupt wire index. (XDMA >> driver determines how system IRQs are mapped to DMA channels and user >> logic wires) >> >>              irq: IRQ number returned for registering interrupt >> handler (request_irq()) or passing to existing platform driver. >> >>      xdma_disable_user_irq(struct platform_device *pdev, u32 >> user_irq_index) >> >> Does this make sense to you? >> > > I think even the "irq" parameter in the enable function is surplus as > the parent driver (the driver of the actual PCIe card) knows* what PCI > irq he has to allocate without XDMA providing the number. > > xdma_enable_user_irq(struct platform_device *pdev, u32 user_irq_index); > xdma_disable_user_irq(struct platform_device *pdev, u32 user_irq_index); > > should be all that is needed. > > M. > > * something like: > pci_irq_vector((pdev), PCI_BAR_ID) + NUM_C2H_CHANNELS + NUM_H2C_CHANNELS > can be used from the PCIe driver How does parent driver know the first few vectors will be assigned to DMA channel?  Parent diver should not assume the first (NUM_C2H_CHANNELS+NUM_H2C_CHANNELS) are for DMA channel. Parent driver passes the system IRQ range  to XDMA driver, and only XDMA driver knows what IRQs are used by DMA channel and what IRQs are mapped to user logic wires. I would keep the "u32 *irq" argument. Thanks, Lizhi