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client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by CH1PEPF0000A347.mail.protection.outlook.com (10.167.244.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.71.7 via Frontend Transport; Wed, 27 May 2026 00:05:01 +0000 Received: from localhost (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.41; Tue, 26 May 2026 19:05:00 -0500 From: Nathan Lynch To: , Nathan Lynch via B4 Relay CC: , , , Subject: Re: [PATCH v2 06/23] dmaengine: sdxi: Allocate DMA pools In-Reply-To: <20260513013053.5F1E1C2BCB0@smtp.kernel.org> References: <20260511-sdxi-base-v2-6-889cfed17e3f@amd.com> <20260513013053.5F1E1C2BCB0@smtp.kernel.org> Date: Tue, 26 May 2026 19:05:00 -0500 Message-ID: <877bop90pf.fsf@amd.com> Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: knMBiANqy3r0pVqxWbh34kmdHzuzn4SmkIaYABKOUaksVPGNVNTkuhEA//Mc3qiujKLHembfLpztcV0UtfwMQxVwxT6ZLc7gpbwGkOiQGOuCRfoJcWKBjSRGBNhAbLZO7eYfqejK/0XPtEa+4ypGewGd/XYaN/7W28LUfbRHTr4OJZWqGCkO+knufSsYOEMSACeR6sdgbxQxbGhHl5L9IfaiKp+hohE6w6MJvUEFg6SVS8cCVh2Z4SmLXivzFh5EEFCucD80DBT7wJUUAKkObrK9F2m+XvpGRqVnVwu7U1E4cR15tu/plDsoc9ar6TCcBspMPgRc3i5wcelRoZQ28GbET+ATcJEAsmBbog3dR8Tzn2FdXPnyoYMNIYXnuQR+SMqnuhJWVglpuAcexnG8kwfjRZnYorZhcELD+jbvgO0fRZ2zBrjX2Y4VIZu6Rz4H X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 May 2026 00:05:01.2180 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fe67452d-f58d-407e-b054-08debb8398d6 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000A347.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA5PPF634736581 sashiko-bot@kernel.org writes: > Thank you for your contribution! Sashiko AI review found 2 potential issu= e(s) to consider: > - [High] Unnecessary use of `__packed` attribute on naturally aligned DMA= structures reduces their assumed alignment to 1 byte, risking torn reads/w= rites. > - [Medium] `cxt_ctl_pool` has a hardcoded alignment of 64 bytes instead o= f `max(size, SMP_CACHE_BYTES)`, leading to potential cacheline sharing. > -- > > commit 12aa7b8ec291c34d27a87b91722b70b67d211aa3 > Author: Nathan Lynch > > dmaengine: sdxi: Allocate DMA pools > > This commit introduces C structures for SDXI context control, context sta= tus, > and completion status blocks. It also creates a DMA pool for each of these > objects as well as write indexes, aiming to align them to avoid cacheline > sharing. > >> diff --git a/drivers/dma/sdxi/device.c b/drivers/dma/sdxi/device.c >> index 6a2204ff7fdee..851e73597c22b 100644 >> --- a/drivers/dma/sdxi/device.c >> +++ b/drivers/dma/sdxi/device.c > > [ ... ] > >> @@ -211,6 +214,43 @@ static int sdxi_fn_activate(struct sdxi_dev *sdxi) >> return 0; >> } >>=20=20 >> +static int sdxi_device_init(struct sdxi_dev *sdxi) >> +{ >> + struct device *dev =3D sdxi->dev; >> + size_t size, align; >> + int err; >> + >> + size =3D sizeof(__le64); >> + align =3D max(size, SMP_CACHE_BYTES); >> + sdxi->write_index_pool =3D dmam_pool_create("Write_Index", dev, size, >> + align, 0); >> + if (!sdxi->write_index_pool) >> + return -ENOMEM; >> + >> + size =3D sizeof(struct sdxi_cxt_sts); >> + align =3D max(size, SMP_CACHE_BYTES); >> + sdxi->cxt_sts_pool =3D dmam_pool_create("CXT_STS", dev, size, align, 0= ); >> + if (!sdxi->cxt_sts_pool) >> + return -ENOMEM; >> + >> + size =3D align =3D sizeof(struct sdxi_cxt_ctl); >> + sdxi->cxt_ctl_pool =3D dmam_pool_create("CXT_CTL", dev, size, align, 0= ); > > The commit message states that frequently-updated objects are aligned to = avoid > cacheline sharing. Does hardcoding the alignment to sizeof(struct sdxi_cx= t_ctl) > risk cacheline sharing on architectures where SMP_CACHE_BYTES is 128? > > Should this use max(size, SMP_CACHE_BYTES) like the other pools? No, sdxi_cxt_ctl is not one of the control structures we expect to be frequently updated, but I suppose this could be made more clear in the commit message or comments. > >> + if (!sdxi->cxt_ctl_pool) >> + return -ENOMEM; > > [ ... ] > >> diff --git a/drivers/dma/sdxi/hw.h b/drivers/dma/sdxi/hw.h >> index df520ca7792bf..846c671c423f5 100644 >> --- a/drivers/dma/sdxi/hw.h >> +++ b/drivers/dma/sdxi/hw.h > > [ ... ] > >> +/* SDXI 1.0 Table 3-4: Context Control (CXT_CTL) */ >> +struct sdxi_cxt_ctl { >> + __le64 ds_ring_ptr; >> + __le32 ds_ring_sz; >> + __u8 rsvd_0[4]; >> + __le64 cxt_sts_ptr; >> + __le64 write_index_ptr; >> + __u8 rsvd_1[32]; >> +} __packed; > > These structures appear to be naturally aligned and padded properly. Does > applying the __packed attribute without an explicit __aligned() attribute > force the compiler to assume 1-byte alignment? > > Could this lead to the compiler synthesizing multiple byte-wise or narrow= er > memory accesses for 32-bit or 64-bit fields when they are read or written, > potentially causing torn reads or writes if the hardware lacks native > unaligned access support? Valid -- I'll add the aligned attributes throughout (I want to continue using packed to prevent inadvertent padding). >> +static_assert(sizeof(struct sdxi_cxt_ctl) =3D=3D 64); >> + >> +/* SDXI 1.0 Table 3-5: Context Status (CXT_STS) */ >> +struct sdxi_cxt_sts { >> + __u8 state; >> + __u8 misc0; >> + __u8 rsvd_0[6]; >> + __le64 read_index; >> +} __packed; >> +static_assert(sizeof(struct sdxi_cxt_sts) =3D=3D 16); >> + >> +/* SDXI 1.0 Table 6-4: CST_BLK (Completion Status Block) */ >> +struct sdxi_cst_blk { >> + __le64 signal; >> + __le32 flags; >> + __u8 rsvd_0[20]; >> +} __packed; >> +static_assert(sizeof(struct sdxi_cst_blk) =3D=3D 32); > > --=20 > Sashiko AI review =C2=B7 https://sashiko.dev/#/patchset/20260511-sdxi-bas= e-v2-0-889cfed17e3f@amd.com?part=3D6