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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: UB2AZhX7SlZHPWhJS2OpaERb+EdENFyZCT/F7T0mOIBJeG6UJP/MlOfnVycOO8OEgfSxuqgI9I4Mlb3IVlvW24blnwpsXKMo7EDVEaT3oLe5yicQcXgRhEk0X9KhZ9nCR6GppO4qv786IxCrpmpjA1avCevNalkV0Tausr9wvYzwYV9iEwe/2R+H/ODGFoZDopLfIrkDwxqFLFjQKMIYzvbtCKkWWs6XtlLaKbHb1CHbQMAIRP2u1Ec2CbipsoxxxUHW0pyoUfjT3WPYJ+pAj1yP3LdFQd+i+J8CMkod29a5PPyFUrpD3V6fM7I70e1fIDcvmTETnZhjm3MHtCEMKtlpQY2m4io+oFV8odZShMFly6U26hZZrVnWSnHE94EjiQ+zvRA68re0RHYNpdNU4ayIvbpXoZDW0G15HZgO34/ueOEuCxuhnbgQfvCfNIxO X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 May 2026 23:44:12.5214 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 818b5630-c2b0-424d-da6b-08debb80b093 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003F68.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH1PPF5EBD457EF sashiko-bot@kernel.org writes: > Thank you for your contribution! Sashiko AI review found 2 potential issu= e(s) to consider: > - [Medium] PCI_CLASS_ACCELERATOR_SDXI is incorrectly defined as a 24-bit = value instead of a standard 16-bit sub-class code. > - [Low] The newly added PCI_CLASS_ACCELERATOR_SDXI class code is missing = from the Rust PCI class bindings. > -- > > commit 5c21a6a19a3c154b4d13c65d1905d5ed4e273dd8 > Author: Nathan Lynch > > PCI: Add SNIA SDXI accelerator sub-class > > This commit adds the sub-class code for the SNIA Smart Data Accelerator > Interface (SDXI) to the PCI IDs list. > >> diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h >> index 24cb42f66e4b6..83ab3f27eb5a2 100644 >> --- a/include/linux/pci_ids.h >> +++ b/include/linux/pci_ids.h >> @@ -154,6 +154,7 @@ >>=20=20 >> #define PCI_BASE_CLASS_ACCELERATOR 0x12 >> #define PCI_CLASS_ACCELERATOR_PROCESSING 0x1200 >> +#define PCI_CLASS_ACCELERATOR_SDXI 0x120100 > > The commit message mentions adding a sub-class code, but is it expected to > define this as a 24-bit value? > > Other generic sub-class macros in this file are standard 16-bit constants, > like the adjacent PCI_CLASS_ACCELERATOR_PROCESSING (0x1200). Drivers > traditionally apply an 8-bit left shift to them when populating ID tables: > > .class =3D PCI_CLASS_ACCELERATOR_SDXI << 8 > > If this standard idiom is used with a 24-bit macro, it will result in a > malformed 32-bit class code (0x12010000) and break device matching. Should > this be defined as 0x1201 instead? I had wondered about whether to follow this convention but I didn't see a strong reason for it. I'll do it if that's what maintainers want. > Additionally, does this new class code need to be added to the Rust PCI c= lass > bindings? It appears to be missing from the define_all_pci_classes! macro= in > rust/kernel/pci/id.rs, which explicitly mirrors these C macros to expose > them to Rust drivers. Seems like a reasonable suggestion. > > --=20 > Sashiko AI review =C2=B7 https://sashiko.dev/#/patchset/20260511-sdxi-bas= e-v2-0-889cfed17e3f@amd.com?part=3D1