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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa20df1b5eesm211019666b.26.2024.11.15.11.23.04 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 15 Nov 2024 11:23:06 -0800 (PST) Message-ID: <87cc1f1e-85d2-40cb-b3b3-8935004f4f98@oss.qualcomm.com> Date: Fri, 15 Nov 2024 20:23:04 +0100 Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 2/4] dmaengine: gpi: Add Lock and Unlock TRE support to access I2C exclusively To: Mukesh Kumar Savaliya , konrad.dybcio@linaro.org, andersson@kernel.org, andi.shyti@kernel.org, linux-arm-msm@vger.kernel.org, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, conor+dt@kernel.org, agross@kernel.org, devicetree@vger.kernel.org, vkoul@kernel.org, linux@treblig.org, dan.carpenter@linaro.org, Frank.Li@nxp.com, konradybcio@kernel.org, bryan.odonoghue@linaro.org, krzk+dt@kernel.org, robh@kernel.org Cc: quic_vdadhani@quicinc.com References: <20241113161413.3821858-1-quic_msavaliy@quicinc.com> <20241113161413.3821858-3-quic_msavaliy@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20241113161413.3821858-3-quic_msavaliy@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: Hn1YcYU5li3LrFX1t5rSiZrmkpNDmWns X-Proofpoint-ORIG-GUID: Hn1YcYU5li3LrFX1t5rSiZrmkpNDmWns X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 suspectscore=0 clxscore=1015 bulkscore=0 impostorscore=0 adultscore=0 malwarescore=0 mlxlogscore=999 lowpriorityscore=0 spamscore=0 phishscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411150163 On 13.11.2024 5:14 PM, Mukesh Kumar Savaliya wrote: > GSI DMA provides specific TREs(Transfer ring element) namely Lock and > Unlock TRE. It provides mutually exclusive access to I2C controller from > any of the processor(Apps,ADSP). Lock prevents other subsystems from > concurrently performing DMA transfers and avoids disturbance to data path. > Basically for shared I2C usecase, lock the SE(Serial Engine) for one of > the processor, complete the transfer, unlock the SE. > > Apply Lock TRE for the first transfer of shared SE and Apply Unlock > TRE for the last transfer. > > Also change MAX_TRE macro to 5 from 3 because of the two additional TREs. > > Signed-off-by: Mukesh Kumar Savaliya > --- > drivers/dma/qcom/gpi.c | 37 +++++++++++++++++++++++++++++++- > include/linux/dma/qcom-gpi-dma.h | 6 ++++++ > 2 files changed, 42 insertions(+), 1 deletion(-) > > diff --git a/drivers/dma/qcom/gpi.c b/drivers/dma/qcom/gpi.c > index 52a7c8f2498f..c9e71c576680 100644 > --- a/drivers/dma/qcom/gpi.c > +++ b/drivers/dma/qcom/gpi.c > @@ -2,6 +2,7 @@ > /* > * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. > * Copyright (c) 2020, Linaro Limited > + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. > */ > > #include > @@ -65,6 +66,14 @@ > /* DMA TRE */ > #define TRE_DMA_LEN GENMASK(23, 0) > > +/* Lock TRE */ > +#define TRE_LOCK BIT(0) > +#define TRE_MINOR_TYPE GENMASK(19, 16) > +#define TRE_MAJOR_TYPE GENMASK(23, 20) > + > +/* Unlock TRE */ > +#define TRE_I2C_UNLOCK BIT(8) So the lock is generic.. I'd then expect the unlock to be generic, too? > + > /* Register offsets from gpi-top */ > #define GPII_n_CH_k_CNTXT_0_OFFS(n, k) (0x20000 + (0x4000 * (n)) + (0x80 * (k))) > #define GPII_n_CH_k_CNTXT_0_EL_SIZE GENMASK(31, 24) > @@ -516,7 +525,7 @@ struct gpii { > bool ieob_set; > }; > > -#define MAX_TRE 3 > +#define MAX_TRE 5 > > struct gpi_desc { > struct virt_dma_desc vd; > @@ -1637,6 +1646,19 @@ static int gpi_create_i2c_tre(struct gchan *chan, struct gpi_desc *desc, > struct gpi_tre *tre; > unsigned int i; > > + /* create lock tre for first tranfser */ > + if (i2c->shared_se && i2c->first_msg) { Does the first/last logic handle errors well? i.e. what if we have >= 3 transfers and: 1) the first transfer succeeds but the last doesn't 2) the first transfer succeeds, the second one doesn't and the lock is submitted again 3) the unlock never suceeds Konrad