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Mon, 23 Mar 2026 02:33:24 -0700 (PDT) Received: from [192.168.1.187] ([148.63.225.166]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48700524864sm98310685e9.5.2026.03.23.02.33.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Mar 2026 02:33:24 -0700 (PDT) Message-ID: <8b6cd66550d7c3cbee0fe1f488d87f00beef12a9.camel@gmail.com> Subject: Re: [PATCH v2 0/5] dmaengine: dma-axi-dmac: Add cyclic transfer support and graceful termination From: Nuno =?ISO-8859-1?Q?S=E1?= To: Vinod Koul Cc: dmaengine@vger.kernel.org, Nuno =?ISO-8859-1?Q?S=E1?= , Lars-Peter Clausen , Frank Li Date: Mon, 23 Mar 2026 09:34:10 +0000 In-Reply-To: References: <20260303-axi-dac-cyclic-support-v2-0-0db27b4be95a@analog.com> <177304239096.87946.15531982345548560058.b4-ty@kernel.org> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.58.3 Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Tue, 2026-03-17 at 15:39 +0530, Vinod Koul wrote: > On 09-03-26, 13:30, Nuno S=C3=A1 wrote: > > On Mon, 2026-03-09 at 08:46 +0100, Vinod Koul wrote: > > Thanks for applying the patches. Since I have you here and if you have = 5 min I would like to > > ask you for some clarifications. It seems there's a bit of a confusion = regarding src_addr_widths > > and dst_addr_widths. For instance the docs say the following: > >=20 > > " bit mask of src addr widths the channel supports. > > Width is specified in bytes, e.g. for a channel supporting > > a width of 4 the mask should have BIT(4) set." > >=20 > > And I suspect that BIT(4) is leading into some confusion. Like, if I ha= ve a width of 4, then my > > mask should look like 0x04 and not 0x20, right? Like the code in [1] lo= oks suspicious to me... > > And > > it seems that pattern is followed in a lot of other places. If I look a= t [2], then it looks more > > with what I would expect. > >=20 > > Like, if the correct way is 1), then it means that 64bytes is not reall= y possible right now > > given > > that BIT(64) is UB and that looks a bit limitating and odd to me. That = and given that the > > AXI_DMAC > > might also suffer from a, possible bug, made me want to clarify this. >=20 > If you look at the field it documents "@src_addr_width: this is the width= in bytes of the source > (RX) > =C2=A0* register where DMA data shall be read. If the source is memory th= is > =C2=A0* may be ignored depending on architecture. Legal values: 1, 2, 3, = 4, > =C2=A0* 8, 16, 32, 64, 128." Yeah, I figured. It seems some drivers are using the enum directly as the m= ask instead for BIT(x). >=20 > We cant have bitmask as 64bit wont work! So I guess lets fix it I do have a working patch locally. I'll send it later this week. - Nuno S=C3=A1