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Thu, 18 Jun 2026 11:51:05 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1781776267; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=W6xJzhq3eQ/1H8oHvoBYc8KIhlbLCwKv1mLFAll1qjs=; b=emRJWnykeDSuP1Wptma20OiUQCWd8ohdbN2DaEJ1THnFKmpKMSTDUmLHfRxjjNpc0hyWa1 QloUJLZ6rmVSTHyuq1hSOE8XJpamQUjMZgbig8oYUR4VKdZ+9CYmcz2pdc3Tv7HxjZheSs fFyQUU+Mvy4D1Br6OMhcg9iErAmspJZq4F/cRGWd97Jr/c/1EnUv8b7/Azt1ExIYxR9f+f 2OLKsY2VcjH15kPRZaBdQsYixmTaHBizWWegavfNNdZyDHvVfy2kUkHmkdFrsODgPBirTA E/FNE4nNTKp4iiuSmeeyTx/l3zeS7TKHdtzB/EMi9gTJMnyx5iiLo4ouszANdg== From: =?UTF-8?B?QmVub8OudA==?= Monin To: Frank Li Cc: Vinod Koul , Thomas Petazzoni , Frank Li , imx@lists.linux.dev, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v4 2/2] dmaengine: fsl-edma: Support dynamic scatter/gather chaining Date: Thu, 18 Jun 2026 11:49:06 +0200 Message-ID: <8kDwWenCRx-QFWAJA2KyZQ@bootlin.com> In-Reply-To: References: <20260518-fsl-edma-dyn-sg-v4-0-8ce7d95b1ce9@bootlin.com> <20260518-fsl-edma-dyn-sg-v4-2-8ce7d95b1ce9@bootlin.com> Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" X-Last-TLS-Session-Version: TLSv1.3 On Friday, 5 June 2026 at 00:01:13 CEST, Frank Li wrote: > On Mon, May 18, 2026 at 02:36:45PM +0200, Beno=C3=AEt Monin wrote: [...] > > +static void fsl_edma_link_sg(struct fsl_edma_chan *fsl_chan, struct fs= l_edma_desc *fsl_desc) > > +{ > > + u32 flags =3D fsl_edma_drvflags(fsl_chan); > > + struct fsl_edma_hw_tcd *last_tcd; > > + struct fsl_edma_desc *prev_desc; > > + struct virt_dma_desc *vdesc; > > + u16 csr; > > + > > + lockdep_assert_held(&fsl_chan->vchan.lock); > > + > > + if (!(flags & FSL_EDMA_DRV_SPLIT_REG)) > > + return; > > + > > + vdesc =3D list_last_entry_or_null(&fsl_chan->vchan.desc_submitted, > > + struct virt_dma_desc, node); > > + if (!vdesc) > > + vdesc =3D list_last_entry_or_null(&fsl_chan->vchan.desc_issued, > > + struct virt_dma_desc, node); > > + if (!vdesc) > > + return; > > + > > + prev_desc =3D to_fsl_edma_desc(vdesc); > > + last_tcd =3D prev_desc->tcd[prev_desc->n_tcds - 1].vtcd; > > + > > + csr =3D fsl_edma_get_tcd_to_cpu(fsl_chan, last_tcd, csr); > > + if (!(csr & EDMA_TCD_CSR_D_REQ)) > > + return; > > + > > + fsl_edma_set_tcd_to_le(fsl_chan, last_tcd, fsl_desc->tcd[0].ptcd, dla= st_sga); > > + > > + csr &=3D ~EDMA_TCD_CSR_D_REQ; > > + csr |=3D EDMA_TCD_CSR_E_SG; >=20 > suppose here need dma_wmb() to make sure dlast_sga happen before csr. >=20 Yes, I will add it. > I remember ask dma risk condition problem, but I forget detail. >=20 > TCD1 > TCD2 > TCD3 (last one), >=20 > If DMAengine already load TCD3 to register and moving data, >=20 > You update TCD3's dlast_sga? Does DMA engine fetch again TCD3 to get > updated dlast_sga? >=20 If the DMAengine already fetched TCD3 from the main memory, then the changes done to dlast_sga and csr in memory will be ignored. In that case, we are back to the current operation. After handling TCD3, the DMAengine will raise the end-of-transfer interrupt, the channel will be set to DMA_COMPLETE, then the call to fsl_edma_xfer_desc() will re-enable the channel with the next issued descriptor. Best regards, =2D-=20 Beno=C3=AEt Monin, Bootlin Embedded Linux and Kernel engineering https://bootlin.com