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Wed, 25 Mar 2026 06:05:48 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 222.71.101.198) smtp.mailfrom=cixtech.com; dkim=none (message not signed) header.d=none;dmarc=bestguesspass action=none header.from=cixtech.com; Received-SPF: Pass (protection.outlook.com: domain of cixtech.com designates 222.71.101.198 as permitted sender) receiver=protection.outlook.com; client-ip=222.71.101.198; helo=smtprelay.cixcomputing.com; pr=C Received: from smtprelay.cixcomputing.com (222.71.101.198) by TY2PEPF0000AB88.mail.protection.outlook.com (10.167.253.11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9723.19 via Frontend Transport; Wed, 25 Mar 2026 06:05:22 +0000 Received: from [172.20.96.43] (unknown [172.20.96.43]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id 40C4B4126F98; Wed, 25 Mar 2026 14:05:21 +0800 (CST) Message-ID: <96077d03-e2b9-4f7a-a8b6-c5bc762e771b@cixtech.com> Date: Wed, 25 Mar 2026 14:05:20 +0800 Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 1/3] dt-bindings: dma: arm-dma350: document generic and combined IRQ topologies To: Robin Murphy , peter.chen@cixtech.com, fugang.duan@cixtech.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, vkoul@kernel.org, ychuang3@nuvoton.com, schung@nuvoton.com, Frank.Li@kernel.org Cc: dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, cix-kernel-upstream@cixtech.com, linux-arm-kernel@lists.infradead.org References: <20260323114822.1925869-1-jun.guo@cixtech.com> <20260323114822.1925869-2-jun.guo@cixtech.com> Content-Language: en-US From: Jun Guo In-Reply-To: Content-Type: text/plain; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: ugPHeeph6Eh/ERuzma0V292FdoYvsylTkW2HRapMeJsq/W1u/Ybe2clxaZywhsqpBqY2N6sg21sn8TRWPthu23cgx08QZvrr0TM5x4aa83e9c8daQ8lHLB/S+IrSjb9vo3aPcL3J8CsozePPz/yLxwOJGLc9DnTfVaGqaajRJAf9tgDeaZIPzPOZTrGjRtfGtXOh7X+FAgFwAVHAMg8sgrsZNC1iuWiTRvOQLUBJqRcZ7j7WYKdtVStAR+9ajB3p0yGUEib+ge0vTtYXundIchV/AMVwQs1XYvyO9grjddT8q1VeeMqHRP5dJvi6Je7YhpO8XrG//rYVU5X4DifJ6BcJ4s1E5ajaOWi1Cb6Yt4In3KXFiiOlK4xaCHXLtUi8NYaU/MmbrT0dRUXFAx+qxZoES58cbBmL1e5uvGEq4GVRiU5f9MeC4eseGXrJJR82 X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Mar 2026 06:05:22.8039 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c9198cf9-16c7-4928-7f34-08de8a34806c X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: TY2PEPF0000AB88.apcprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PS1PPF4E5A438BE On 3/24/2026 8:04 PM, Robin Murphy wrote: > [Some people who received this message don't often get email from > robin.murphy@arm.com. Learn why this is important at https://aka.ms/ > LearnAboutSenderIdentification ] > > EXTERNAL EMAIL > > On 2026-03-23 11:48 am, Jun Guo wrote: >> Update the DMA-350 DT binding to match the current driver behavior. >> >> Allow both: >> - "arm,dma-350" as the generic compatible, and >> - "cix,sky1-dma-350", "arm,dma-350" for SoC-specific fallback usage. >> >> Also document interrupt topology variants supported by hardware >> integration: >> - one combined interrupt for all channels, or >> - one interrupt per channel (up to 8 channels). > > To repeat myself for the 3rd time, this is at best unnecessary, and at > worst arguably wrong. Here's an example of a system which happens to use > the combined interrupt from another IP block which also offers both > options: > > https://web.git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/ > tree/arch/arm64/boot/dts/freescale/imx8qm.dtsi#n279 > > Same thing here; each channel is a distinct interrupt source, so it is > perfectly honest to describe that consistently in DT, regardless of > whether or not the interrupt signals are still distinct by the time they > reach the interrupt controller. > > Furthermore, in this case the IRQ_COMB_NONSEC interrupt actually has > additional functionality beyond just being a mux of the individual > IRQ_CHANNEL interrupts. So although Linux probably won't ever care, if > it's going to be in the DT binding then it should really be distinct > from the channel interrupts anyway, since systems could well wire them > *all* up, and an OS could choose to use the IRQ_CHANNEL outputs directly > for individual channel completion/error status, while also using the > IRQ_COMB_NONSEC just for its overall INTR_ALLCH{STOPPED,PAUSED,IDLE} > status. > > If you only want to make your thing work in Linux, all that is needed is > a 1-line change in the driver to enable the INTR_ANYCHINTR bit (which as > I've also said before, we can do unconditionally because we're *not* > using the other INTR_ALLCH stuff), and to write your DT using the > existing binding. "One interrupt per channel" already carries no > expectation that they all have to be *different* interrupts. > You've indeed said this for the third time, but I did not ignore your comments earlier. I carefully reviewed your feedback on both the V1 and V2 patches. However, since your initial comments were not as detailed, I promptly replied to your emails hoping to discuss them further. Unfortunately, you did not respond to either of my follow-up emails, so I proceeded with submitting the current version of the patch. You can refer to the records here: https://lore.kernel.org/all/20251216123026.3519923-2-jun.guo@cixtech.com/ or https://lore.kernel.org/all/20251117015943.2858-3-jun.guo@cixtech.com/ Now, with this latest email, I clearly understand the point you are making. I will revise and resubmit the patch accordingly, which should result in a much more concise version. Thank you for your reply. Best regards, Jun