DMA Engine development
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 messages from 2026-06-20 17:16:20 to 2026-06-20 20:47:39 UTC [more...]

[PATCH RESEND 0/3] dmaengine: xilinx_dma: Fixes and optimizations for AXIDMA and MCDMA channel management
 2026-06-20 20:47 UTC  (7+ messages)
` [PATCH RESEND 1/3] dmaengine: xilinx_dma: Fix channel idle state management in AXIDMA and MCDMA interrupt handlers
` [PATCH RESEND 2/3] dmaengine: xilinx_dma: Enable transfer chaining for AXIDMA and MCDMA by removing idle restriction
` [PATCH RESEND 3/3] dmaengine: xilinx_dma: Optimize control register write and channel start logic for AXIDMA and MCDMA in corresponding start_transfer()

[PATCH v3 00/13] dmaengine: dw-edma: Prepare for PCI EP DMA (part 1/3)
 2026-06-20 17:25 UTC  (9+ messages)
` [PATCH v3 03/13] dmaengine: dw-edma: Add delegated channel request helpers
` [PATCH v3 04/13] dmaengine: dw-edma: Initialize IRQ data before requesting IRQs
` [PATCH v3 10/13] dmaengine: dw-edma-pcie: Add register offset match flag
` [PATCH v3 13/13] dmaengine: dw-edma-pcie: Add chip flags to match data


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