messages from 2026-06-23 08:47:02 to 2026-06-25 16:22:02 UTC [more...]
[PATCH] dt-bindings: dma: xlnx,axi-dma: Restore xlnx,flush-fsync as u32
2026-06-25 16:21 UTC (2+ messages)
[PATCH] dmaengine: mediatek: hsdma: fix runtime PM leak on init failure
2026-06-25 16:03 UTC (3+ messages)
[PATCH RESEND v4] dmaengine: dw-edma: Enable HDMA 64R/W Channels
2026-06-25 15:56 UTC (4+ messages)
[PATCH v3 0/5] dmaengine: mcf-edma: fix 64-channel handling and modernize IRQ setup
2026-06-25 15:33 UTC (15+ messages)
` [PATCH v3 1/5] dmaengine: fsl-edma: Move error handler out of header file
` [PATCH v3 2/5] dmaengine: fsl-edma: Add FSL_EDMA_DRV_MCF flag for ColdFire eDMA
` [PATCH v3 3/5] dmaengine: mcf-edma: Fix interrupt handler for 64 DMA channels
` [PATCH v3 4/5] dmaengine: mcf-edma: Fix error handler for all "
` [PATCH v3 5/5] dmaengine: mcf-edma: Use devm for per-channel IRQ registration
[PATCH] dmaengine: qcom: gpi: correct channel name in error path
2026-06-25 15:01 UTC (3+ messages)
[PATCH 1/2] dmaengine: mpc512x: fix dead empty check in mpc_dma_prep_slave_sg()
2026-06-25 11:35 UTC (3+ messages)
` [PATCH v2] "
[PATCH RFC 0/3] dmaengine: Support address bus widths of 32 bytes and above
2026-06-25 8:54 UTC (19+ messages)
` [PATCH RFC 2/3] dmaengine: dma-axi-dmac: Switch to bitmap-based address width masks
[PATCH v6 00/10] Add GPCDMA support in Tegra264
2026-06-24 12:35 UTC (5+ messages)
` [PATCH v6 02/10] arm64: tegra: Remove fallback compatible for GPCDMA
[PATCH] dmaengine: dw-axi-dmac: Fix cfgr_clk leak in resume error path
2026-06-24 7:54 UTC (2+ messages)
[PATCH] MAINTAINERS: altera-msgdma: replace maintainer
2026-06-24 5:49 UTC
[PATCH RESEND 0/3] dmaengine: xilinx_dma: Fixes and optimizations for AXIDMA and MCDMA channel management
2026-06-23 18:46 UTC (8+ messages)
` [PATCH RESEND 1/3] dmaengine: xilinx_dma: Fix channel idle state management in AXIDMA and MCDMA interrupt handlers
` [PATCH RESEND 2/3] dmaengine: xilinx_dma: Enable transfer chaining for AXIDMA and MCDMA by removing idle restriction
` [PATCH RESEND 3/3] dmaengine: xilinx_dma: Optimize control register write and channel start logic for AXIDMA and MCDMA in corresponding start_transfer()
SDXI on AMD EPYC (in relation to Nathan’s SDXI dmaengine patchset)
2026-06-23 14:32 UTC (3+ messages)
[PATCH RESEND v4] dmaengine: dw-edma: Enable HDMA 64R/W Channels
2026-06-23 11:39 UTC (3+ messages)
[PATCH 00/11] pmdomain: st: ux500: Implement ux500 power domains
2026-06-23 8:46 UTC (3+ messages)
` [PATCH 02/11] dt-bindings: Add the actual power domains on U8500
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