DMA Engine development
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 messages from 2026-06-23 09:50:11 to 2026-06-23 18:47:32 UTC [more...]

[PATCH RESEND 0/3] dmaengine: xilinx_dma: Fixes and optimizations for AXIDMA and MCDMA channel management
 2026-06-23 18:46 UTC  (8+ messages)
` [PATCH RESEND 1/3] dmaengine: xilinx_dma: Fix channel idle state management in AXIDMA and MCDMA interrupt handlers
` [PATCH RESEND 2/3] dmaengine: xilinx_dma: Enable transfer chaining for AXIDMA and MCDMA by removing idle restriction
` [PATCH RESEND 3/3] dmaengine: xilinx_dma: Optimize control register write and channel start logic for AXIDMA and MCDMA in corresponding start_transfer()

[PATCH RFC 0/3] dmaengine: Support address bus widths of 32 bytes and above
 2026-06-23 15:01 UTC  (16+ messages)
` [PATCH RFC 2/3] dmaengine: dma-axi-dmac: Switch to bitmap-based address width masks

SDXI on AMD EPYC (in relation to Nathan’s SDXI dmaengine patchset)
 2026-06-23 14:32 UTC  (3+ messages)

[PATCH v6 00/10] Add GPCDMA support in Tegra264
 2026-06-23 14:02 UTC  (3+ messages)
` [PATCH v6 02/10] arm64: tegra: Remove fallback compatible for GPCDMA

[PATCH RESEND v4] dmaengine: dw-edma: Enable HDMA 64R/W Channels
 2026-06-23 11:41 UTC  (2+ messages)

[PATCH RESEND v4] dmaengine: dw-edma: Enable HDMA 64R/W Channels
 2026-06-23 11:39 UTC  (3+ messages)


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