From: Vinod Koul <vkoul@kernel.org>
To: pandith.n@intel.com
Cc: Eugeniy.Paltsev@synopsys.com, dmaengine@vger.kernel.org,
lakshmi.bai.raja.subramanian@intel.com, kris.pan@intel.com,
mallikarjunappa.sangannavar@intel.com,
Srikanth.Thokala@intel.com
Subject: Re: [PATCH V5 0/3] dmaengine: dw-axi-dmac: support parallel memory <--> peripheral transfers
Date: Mon, 2 Aug 2021 12:20:02 +0530 [thread overview]
Message-ID: <YQeVmuuLBznc9sBv@matsya> (raw)
In-Reply-To: <20210802055454.15192-1-pandith.n@intel.com>
On 02-08-21, 11:24, pandith.n@intel.com wrote:
> From: Pandith N <pandith.n@intel.com>
>
> Added support for multiple DMA_MEM_TO_DEV, DMA_DEV_TO_MEM transfers in
> parallel. Peripherals can use DMA for both transmit and receive
> operations in parallel.
>
> To setup DMA handshaking, the peripheral source number to be programmed
> in respective channel select slot of AXIDMA_CTRL_DMA_HS_SEL. No need to
> check for free slot in dw_axi_dma_set_hw_channel().
>
> The channel slot used in AXIDMA_CTRL_DMA_HS_SEL needs to be set in
> src_per/dst_per of CHx_CFG register
>
> Burst length, DMA HW capability set in dt-binding is now used in driver.
Applied, thanks
--
~Vinod
prev parent reply other threads:[~2021-08-02 6:50 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-02 5:54 [PATCH V5 0/3] dmaengine: dw-axi-dmac: support parallel memory <--> peripheral transfers pandith.n
2021-08-02 5:54 ` [PATCH V5 1/3] dmaengine: dw-axi-dmac: Remove free slot check algorithm in dw_axi_dma_set_hw_channel pandith.n
2021-08-02 5:54 ` [PATCH V5 2/3] dmaengine: dw-axi-dmac: support parallel memory <--> peripheral transfers pandith.n
2021-08-02 5:54 ` [PATCH V5 3/3] dmaengine: dw-axi-dmac: Burst length settings pandith.n
2021-08-02 6:50 ` Vinod Koul [this message]
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