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Fri, 10 Jan 2025 02:29:38 -0800 (PST) Date: Fri, 10 Jan 2025 11:29:33 +0100 From: Stephan Gerhold To: Md Sadre Alam Cc: vkoul@kernel.org, robin.murphy@arm.com, u.kleine-koenig@baylibre.com, martin.petersen@oracle.com, fenghua.yu@intel.com, av2082000@gmail.com, linux-arm-msm@vger.kernel.org, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, quic_mmanikan@quicinc.com, quic_srichara@quicinc.com, quic_varada@quicinc.com Subject: Re: [PATCH v4] dmaengine: qcom: bam_dma: Avoid writing unavailable register Message-ID: References: <20241220094203.3510335-1-quic_mdalam@quicinc.com> Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20241220094203.3510335-1-quic_mdalam@quicinc.com> On Fri, Dec 20, 2024 at 03:12:03PM +0530, Md Sadre Alam wrote: > Avoid writing unavailable register in BAM-Lite mode. > BAM_DESC_CNT_TRSHLD register is unavailable in BAM-Lite > mode. Its only available in BAM-NDP mode. So only write > this register for clients who is using BAM-NDP. > > Signed-off-by: Md Sadre Alam What are we actually fixing here? Which platform is affected? Is there a crash, reset, or incorrect behavior? We have had this code for years without reported issues, with both BAM-NDP and BAM-Lite instances. The register documentation on APQ8016E documents the BAM_DESC_CNT_TRSHLD register even for the BAM-Lite instance. There is a comment that it doesn't apply to BAM-Lite, but I would expect the written value just ends up being ignored in that case. Also, there is not just BAM-NDP and BAM-Lite, but also plain "BAM". What about that one? Should we write to BAM_DESC_CNT_TRSHLD? > --- > Change in [v4] > > * Added in_range() macro > > Change in [v3] > > * Removed BAM_LITE macro > > * Updated commit message > > * Adjusted if condition check > > * Renamed BAM-NDP macro to BAM_NDP_REVISION_START and > BAM_NDP_REVISION_END > > Change in [v2] > > * Replace 0xff with REVISION_MASK in the statement > bdev->bam_revision = val & REVISION_MASK > > Change in [v1] > > * Added initial patch > > drivers/dma/qcom/bam_dma.c | 24 ++++++++++++++++-------- > 1 file changed, 16 insertions(+), 8 deletions(-) > > diff --git a/drivers/dma/qcom/bam_dma.c b/drivers/dma/qcom/bam_dma.c > index bbc3276992bb..c14557efd577 100644 > --- a/drivers/dma/qcom/bam_dma.c > +++ b/drivers/dma/qcom/bam_dma.c > @@ -59,6 +59,9 @@ struct bam_desc_hw { > #define DESC_FLAG_NWD BIT(12) > #define DESC_FLAG_CMD BIT(11) > > +#define BAM_NDP_REVISION_START 0x20 > +#define BAM_NDP_REVISION_END 0x27 > + Are you sure this covers all SoCs we support upstream? If one of the older or newer supported SoCs uses a value outside of this range, it will now be missing the register write. Thanks, Stephan