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Mon, 22 Dec 2025 00:14:12 -0800 (PST) X-Google-Smtp-Source: AGHT+IG1Go09mxe6FptC6uL4OomBUKer2vZ4FaNIffkFWpnND+g9IVqxiqRcg2zZV/2/WJ8KZ0XTqQ== X-Received: by 2002:a17:90b:1d83:b0:32a:34d8:33d3 with SMTP id 98e67ed59e1d1-34e91f749d8mr8077421a91.0.1766391251826; Mon, 22 Dec 2025 00:14:11 -0800 (PST) Received: from [10.218.35.45] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-34e70dbd618sm12166827a91.12.2025.12.22.00.14.04 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 22 Dec 2025 00:14:11 -0800 (PST) Message-ID: Date: Mon, 22 Dec 2025 13:44:02 +0530 Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC PATCH v2 19/27] PCI: dwc: ep: Cache MSI outbound iATU mapping To: Niklas Cassel Cc: Koichiro Den , ntb@lists.linux.dev, linux-pci@vger.kernel.org, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, Frank.Li@nxp.com, mani@kernel.org, kwilczynski@kernel.org, kishon@kernel.org, bhelgaas@google.com, corbet@lwn.net, vkoul@kernel.org, jdmason@kudzu.us, dave.jiang@intel.com, allenbh@gmail.com, Basavaraj.Natikar@amd.com, Shyam-sundar.S-k@amd.com, kurt.schwemmer@microsemi.com, logang@deltatee.com, jingoohan1@gmail.com, lpieralisi@kernel.org, robh@kernel.org, jbrunet@baylibre.com, fancer.lancer@gmail.com, arnd@arndb.de, pstanner@redhat.com, elfring@users.sourceforge.net References: <20251129160405.2568284-1-den@valinux.co.jp> <20251129160405.2568284-20-den@valinux.co.jp> <4909f70a-2f65-4cac-96ac-5cd4371bc867@oss.qualcomm.com> Content-Language: en-US From: Krishna Chaitanya Chundru In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjIyMDA3MyBTYWx0ZWRfX28td5LjqKxU9 UVYt7gfA+/Rv6PVOctQjEUlGw7GtmJw4VIdH2PnhShQfgGFLij4JUq1T0EDt1V48v57mUvyMr2l DVTr8slyrkMW4lguDx1biljs/R5EDmFmwL7A7eBLDTJG9LWnC+U8V6oI2icC2qdzMVPR0K8jS5a Oj61d3HqLYxjdMxFkUQJRW0iF7Km8InlN4ljGq30KDMHUAv0xDN1M7RFdccMp0bupq0BsZx26OF V0BZxW3ukBmcDbbLGTIgvaQ/lkj1UQ42Ap5XKXGuJsd2WqSlH+hAoZzrwa1ak+bPq1JWrV76R9s cdulCgZr3rsGgMDV/mAMVC+bp1TcZwiJeha2fZV1b1gX+rSZLwIvWpvUQ2qIX87A3rtet82+CXo u6aOSiY4GYUj9hQKSaSBrVPVb7hD10ec2rBai80c/XpjCi+9vyxICAREsQacETLzSAeVSGbWp20 govOVmCsT1iWqCxgNkg== X-Authority-Analysis: v=2.4 cv=VMnQXtPX c=1 sm=1 tr=0 ts=6948fdd5 cx=c_pps a=UNFcQwm+pnOIJct1K4W+Mw==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=9AdMxfjQAAAA:20 a=VwQbUJbxAAAA:8 a=P-IC7800AAAA:8 a=XlojDObrNaimPXCU0dcA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=uKXjsCUrEbL0IQVhDsJ9:22 a=d3PnA9EDa4IxuAV0gXij:22 a=bA3UWDv6hWIuX7UZL3qL:22 X-Proofpoint-ORIG-GUID: cpiAabBllmwtaXySW2WUUeFzvPk_4csE X-Proofpoint-GUID: cpiAabBllmwtaXySW2WUUeFzvPk_4csE X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-21_05,2025-12-19_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 malwarescore=0 phishscore=0 suspectscore=0 lowpriorityscore=0 spamscore=0 adultscore=0 priorityscore=1501 impostorscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2512220073 On 12/22/2025 1:20 PM, Niklas Cassel wrote: > On Mon, Dec 22, 2025 at 10:40:12AM +0530, Krishna Chaitanya Chundru wrote: >> On 12/8/2025 1:27 PM, Niklas Cassel wrote: >>> On Sun, Nov 30, 2025 at 01:03:57AM +0900, Koichiro Den wrote: >>> >>> I guess the problem is that some EPF drivers, even if only >>> one capability can be enabled (MSI/MSI-X), call both >>> pci_epc_set_msi() and pci_epc_set_msix(), e.g.: >>> https://github.com/torvalds/linux/blob/v6.18/drivers/pci/endpoint/functions/pci-epf-test.c#L969-L987 >>> >>> To fill in the number of MSI/MSI-X irqs. >>> >>> While other EPF drivers only call either pci_epc_set_msi() or >>> pci_epc_set_msix(), depending on the IRQ type that will actually >>> be used: >>> https://github.com/torvalds/linux/blob/v6.18/drivers/nvme/target/pci-epf.c#L2247-L2262 >>> >>> I think both versions is okay, just because the number of IRQs >>> is filled in for both MSI/MSI-X, AFAICT, only one of them will >>> get enabled. >>> >>> >>> I guess it might be hard for an EPC driver to know which capability >>> that is currently enabled, as to enable a capability is only a config >>> space write by the host side. >> As the host is the one which enables MSI/MSIX, it should be better the >> controller >> driver takes this decision and the EPF driver just sends only raise_irq. >> Because technically, host can disable MSI and enable MSIX at runtime also. >> >> In the controller driver,  it can check which is enabled and chose b/w >> MSIX/MSI/Legacy. > I'm not sure if I'm following, but if by "the controller driver", you > mean the EPC driver, and not the host side driver, how can the EPC > driver know how many interrupts a specific EPF driver wants to use? I meant the dwc drivers here. Set msi & set msix still need to called from the EPF driver only to tell how many interrupts they want to configure etc. > > From the kdoc to pci_epc_set_msi(), the nr_irqs parameter is defined as: > @nr_irqs: number of MSI interrupts required by the EPF > https://github.com/torvalds/linux/blob/v6.19-rc2/drivers/pci/endpoint/pci-epc-core.c#L305 > > > Anyway, I posted Koichiro's patch here: > https://lore.kernel.org/linux-pci/20251210071358.2267494-2-cassel@kernel.org/ I will comment on that patch. > > See my comment: > pci-epf-test does change between MSI and MSI-X without calling > dw_pcie_ep_stop(), however, the msg_addr address written by the host > will be the same address, at least when using a Linux host using a DWC > based controller. If another host ends up using different msg_addr for > MSI and MSI-X, then I think that we will need to modify pci-epf-test to > call a function when changing IRQ type, such that pcie-designware-ep.c > can tear down the MSI/MSI-X mapping. Maybe for arm based systems we are getting same address but for x86 based systems it is not guarantee that you will get same address. > So if we want to improve things, I think we need to modify the EPF drivers > to call a function when changing the IRQ type. The EPF driver should know > which IRQ type that is currently in use (see e.g. nvme_epf->irq_type in > drivers/nvme/target/pci-epf.c). My suggestion is let EPF driver call raise_irq with the vector number then the dwc driver can raise IRQ based on which IRQ host enables it. > Additionally, I don't think that the host side should be allowed to change > the IRQ type (using e.g. setpci) when the EPF driver is in a "running state". In the host driver itelf they can choose to change it by using pci_alloc_irq_vectors , Currently it is not present but in future someone can change it, as spec didn't say you can't update it. > I think things will break badly if you e.g. try to do this on an PCIe > connected network card while the network card is in use. I agree on this. I just want to highlight there is possibility of this in future, if someone comes up with a clean logic. - Krishna Chaitanya. > > > Kind regards, > Niklas