Re: [PATCH 1/2] dmaengine: idxd: Expose DSA3.0 capabilities through sysfs

[Yi Sun <yi.sun@intel.com>]

On 13.06.2025 13:59, Dave Jiang wrote:
>
>
>On 6/13/25 9:18 AM, Yi Sun wrote:
>> Introduce sysfs interfaces for 3 new Data Streaming Accelerator (DSA)
>> capability registers (dsacap0-2) to enable userspace awareness of hardware
>> features in DSA version 3 and later devices.
>>
>> Userspace components (e.g. configure libraries, workload Apps) require this
>> information to:
>> 1. Select optimal data transfer strategies based on SGL capabilities
>> 2. Enable hardware-specific optimizations for floating-point operations
>> 3. Configure memory operations with proper numerical handling
>> 4. Verify compute operation compatibility before submitting jobs
>>
>> The output consists of values from the three dsacap registers, concatenated
>> in order and separated by commas.
>>
>> Example:
>> cat /sys/bus/dsa/devices/dsa0/dsacap
>>  0014000e000007aa,00fa01ff01ff03ff,000000000000f18d
>>
>> Signed-off-by: Yi Sun <yi.sun@intel.com>
>> Co-developed-by: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
>> Signed-off-by: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
>
>Would be good to provide a link to the 3.0 spec. Otherwise
>Reviewed-by: Dave Jiang <dave.jiang@intel.com>
>
Sure, will add this link:
https://cdrdv2-public.intel.com/857060/341204-006-intel-data-streaming-accelerator-spec.pdf

Thanks
    --Sun, Yi