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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?nPMBdmcq+2lbRZbOeESVOt5L2w26ekAtkillL/KLicbJAomOurVl8TN6P3Rl?= =?us-ascii?Q?9CRdCD0EhO7REt+b0UKx+5n/z8RsLlEppGu+aqxO73A4bt36rU6JlKnUQCR8?= =?us-ascii?Q?1GM/eKA7ca0AH68YuC6rFEXn/5P0sduGOfRjBPSL8nq1Lm/eoqN5UFcQzUAd?= =?us-ascii?Q?UKlxilfsci1+niq6aT7qUj54YczspVdHOZJeKpVSgE50GYfBO+QQHwPkiSmv?= =?us-ascii?Q?wd94i4vvn8wdMTlUtw3CBEc27NAjepAjx+oEv9gz0tmXdsKZYTCu+hq9s/LX?= =?us-ascii?Q?cWkvJYIBqNr3k4ICyInv0RCv15MJTnNEL6ggsXzmPkPInQxzyfs/EIDEcR1+?= =?us-ascii?Q?ruGy/DkwgzQdhsi+p27/uhD7Nhu5ibydYKpKfXxejEVZqfk1k5qPvOTJ/C3f?= =?us-ascii?Q?my2KumegItsWhsojh2FZFMdsXMqMifPmS6ENk0rofIrT8Y0WybOBQG1Y6R51?= =?us-ascii?Q?zl6ObkC3eGlyJJ2RFnWmDkBWWhXLIvvARQdBv7rNt3FDUWvQ8A0rc+jEQIcL?= =?us-ascii?Q?urbUaGef7c/U968457utyt9Xuvy1QGQqb23cylP1Op/uylERFv/hM58GRTFa?= =?us-ascii?Q?qLO/JloJrWZupLuuh37KRGLHUua2Nth01KueWG8tfNomTloZPuw1oCVDiOrm?= =?us-ascii?Q?TDn9csjj2dDfUQPCHd2F+U2dOm17T/6AEG8Nt5DfWFKrtB0dmmuMo05DCCD2?= =?us-ascii?Q?SiWzzLNOu0bixaam72jcXcmIrgysOjfgrsOwO4qawhkfrjaYf8mhDoohrkV1?= =?us-ascii?Q?vVLyF7+Omy7hQvWah+eLfVh7Guzgma8rEWRVhNe3xKPIzKMy3hMNEm4PYq/D?= =?us-ascii?Q?GReIkwr4c1yLHWeUI3bLB0oo1iPYJfSOyQgrRpSCEKqv9KYczVXvMlkK1T9e?= =?us-ascii?Q?PgqLUAW5ldppPA9o8v4V+ux+rACvdtUkXmB1BOPZ6a/CwihE5Agwq8LE/dv+?= =?us-ascii?Q?w4Jmd2NarPfaMs2fBNs1KSC9j1WyvVMYUcBivSb4o84KqvpyiWdTBhtrkyr4?= =?us-ascii?Q?FdRwujBcwcQv8H+r5/XdTznkFxq/iddSFjNSSQTo8OfSL7nA7XaA36JCAMqP?= =?us-ascii?Q?FwIFXiRfo5KAJIdLU276XlInYDj0udnfUhiqeTmncV4EKBtpeEPQQgcZr5/o?= =?us-ascii?Q?pMmDIX8Zyn6OgFSq2lbS/P33lLYasUHTetugxHYzx0Lw7rqpIxvenaoe2dGs?= =?us-ascii?Q?lrIYRs0IFcM1pebD6n+HxLILtLUPYP7IiynN7d15/oO/LhjX+PDfxV/ai7de?= =?us-ascii?Q?ajs20SAkvvteWflBmZU2/70JZ0F35s/rcH/rLd2UM/kaDK2ZEfrnJItaKSmb?= =?us-ascii?Q?3NRTuNnYliPwhIsY1+RC3tJjNOEcJS+nSjyYCShwcSrVcjW80lQfhLD+I5QG?= =?us-ascii?Q?QSbpNZRemAYDvvo0pYOuIqq4k3of6M/yz6uH7JC69wpDMgS1QccUo/NtShSr?= =?us-ascii?Q?U8DFynaOLy512qPxHykU6H4E0eJergjNWkUBsXsn2xqCAQQn5oxUbZS+3JxX?= =?us-ascii?Q?TDmx31vy4M+/NTXLf6Ic/JAGhuPenVHiK0rhmTf+XeM7ME5mdwDlR2KITge3?= =?us-ascii?Q?uXM/6GbRB5/4r04xprT5Ss8/xfQHH9PyCLWwF6l8?= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 4187a127-97a2-4a78-e9cc-08de310d67e5 X-MS-Exchange-CrossTenant-AuthSource: DU2PR04MB8951.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Dec 2025 19:11:18.2000 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: Wkfd7gMgbEArNa7dYdqPppHl3PTFb3UbwCiV7GIPEzxZnrBIEgi/8/LtYj8thqOgUjuvcCo8SwXKFQMsbsJRSQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU0PR04MB9321 On Sun, Nov 30, 2025 at 01:03:40AM +0900, Koichiro Den wrote: > Introduce new mwN_offset configfs attributes to specify memory window > offsets. This enables mapping multiple windows into a single BAR at This need update documents. But I am not clear how multiple windows map into a single BAR, could you please give me an example, how to config more than 2 memory space to one bar by echo to sys file commands. Frank > arbitrary offsets, improving layout flexibility. > > Signed-off-by: Koichiro Den > --- > drivers/pci/endpoint/functions/pci-epf-vntb.c | 133 ++++++++++++++++-- > 1 file changed, 120 insertions(+), 13 deletions(-) > > diff --git a/drivers/pci/endpoint/functions/pci-epf-vntb.c b/drivers/pci/endpoint/functions/pci-epf-vntb.c > index 6c4c78915970..1ff414703566 100644 > --- a/drivers/pci/endpoint/functions/pci-epf-vntb.c > +++ b/drivers/pci/endpoint/functions/pci-epf-vntb.c > @@ -39,6 +39,7 @@ > #include > #include > #include > +#include > #include > #include > > @@ -111,7 +112,8 @@ struct epf_ntb_ctrl { > u64 addr; > u64 size; > u32 num_mws; > - u32 reserved; > + u32 mw_offset[MAX_MW]; > + u32 mw_size[MAX_MW]; > u32 spad_offset; > u32 spad_count; > u32 db_entry_size; > @@ -128,6 +130,7 @@ struct epf_ntb { > u32 db_count; > u32 spad_count; > u64 mws_size[MAX_MW]; > + u64 mws_offset[MAX_MW]; > atomic64_t db; > u32 vbus_number; > u16 vntb_pid; > @@ -458,6 +461,8 @@ static int epf_ntb_config_spad_bar_alloc(struct epf_ntb *ntb) > > ctrl->spad_count = spad_count; > ctrl->num_mws = ntb->num_mws; > + memset(ctrl->mw_offset, 0, sizeof(ctrl->mw_offset)); > + memset(ctrl->mw_size, 0, sizeof(ctrl->mw_size)); > ntb->spad_size = spad_size; > > ctrl->db_entry_size = sizeof(u32); > @@ -689,15 +694,31 @@ static void epf_ntb_db_bar_clear(struct epf_ntb *ntb) > */ > static int epf_ntb_mw_bar_init(struct epf_ntb *ntb) > { > + struct device *dev = &ntb->epf->dev; > + u64 bar_ends[BAR_5 + 1] = { 0 }; > + unsigned long bars_used = 0; > + enum pci_barno barno; > + u64 off, size, end; > int ret = 0; > int i; > - u64 size; > - enum pci_barno barno; > - struct device *dev = &ntb->epf->dev; > > for (i = 0; i < ntb->num_mws; i++) { > - size = ntb->mws_size[i]; > barno = ntb->epf_ntb_bar[BAR_MW1 + i]; > + off = ntb->mws_offset[i]; > + size = ntb->mws_size[i]; > + end = off + size; > + if (end > bar_ends[barno]) > + bar_ends[barno] = end; > + bars_used |= BIT(barno); > + } > + > + for (barno = BAR_0; barno <= BAR_5; barno++) { > + if (!(bars_used & BIT(barno))) > + continue; > + if (bar_ends[barno] < SZ_4K) > + size = SZ_4K; > + else > + size = roundup_pow_of_two(bar_ends[barno]); > > ntb->epf->bar[barno].barno = barno; > ntb->epf->bar[barno].size = size; > @@ -713,8 +734,12 @@ static int epf_ntb_mw_bar_init(struct epf_ntb *ntb) > &ntb->epf->bar[barno]); > if (ret) { > dev_err(dev, "MW set failed\n"); > - goto err_alloc_mem; > + goto err_set_bar; > } > + } > + > + for (i = 0; i < ntb->num_mws; i++) { > + size = ntb->mws_size[i]; > > /* Allocate EPC outbound memory windows to vpci vntb device */ > ntb->vpci_mw_addr[i] = pci_epc_mem_alloc_addr(ntb->epf->epc, > @@ -723,19 +748,31 @@ static int epf_ntb_mw_bar_init(struct epf_ntb *ntb) > if (!ntb->vpci_mw_addr[i]) { > ret = -ENOMEM; > dev_err(dev, "Failed to allocate source address\n"); > - goto err_set_bar; > + goto err_alloc_mem; > } > } > > + for (i = 0; i < ntb->num_mws; i++) { > + ntb->reg->mw_offset[i] = (u32)ntb->mws_offset[i]; > + ntb->reg->mw_size[i] = (u32)ntb->mws_size[i]; > + } > + > return ret; > > -err_set_bar: > - pci_epc_clear_bar(ntb->epf->epc, > - ntb->epf->func_no, > - ntb->epf->vfunc_no, > - &ntb->epf->bar[barno]); > err_alloc_mem: > - epf_ntb_mw_bar_clear(ntb, i); > + while (--i >= 0) > + pci_epc_mem_free_addr(ntb->epf->epc, > + ntb->vpci_mw_phy[i], > + ntb->vpci_mw_addr[i], > + ntb->mws_size[i]); > +err_set_bar: > + while (--barno >= BAR_0) > + if (bars_used & BIT(barno)) > + pci_epc_clear_bar(ntb->epf->epc, > + ntb->epf->func_no, > + ntb->epf->vfunc_no, > + &ntb->epf->bar[barno]); > + > return ret; > } > > @@ -1039,6 +1076,60 @@ static ssize_t epf_ntb_##_name##_store(struct config_item *item, \ > return len; \ > } > > +#define EPF_NTB_MW_OFF_R(_name) \ > +static ssize_t epf_ntb_##_name##_show(struct config_item *item, \ > + char *page) \ > +{ \ > + struct config_group *group = to_config_group(item); \ > + struct epf_ntb *ntb = to_epf_ntb(group); \ > + struct device *dev = &ntb->epf->dev; \ > + int win_no, idx; \ > + \ > + if (sscanf(#_name, "mw%d_offset", &win_no) != 1) \ > + return -EINVAL; \ > + \ > + idx = win_no - 1; \ > + if (idx < 0 || idx >= ntb->num_mws) { \ > + dev_err(dev, "MW%d out of range (num_mws=%d)\n", \ > + win_no, ntb->num_mws); \ > + return -EINVAL; \ > + } \ > + \ > + idx = array_index_nospec(idx, ntb->num_mws); \ > + return sprintf(page, "%lld\n", ntb->mws_offset[idx]); \ > +} > + > +#define EPF_NTB_MW_OFF_W(_name) \ > +static ssize_t epf_ntb_##_name##_store(struct config_item *item, \ > + const char *page, size_t len) \ > +{ \ > + struct config_group *group = to_config_group(item); \ > + struct epf_ntb *ntb = to_epf_ntb(group); \ > + struct device *dev = &ntb->epf->dev; \ > + int win_no, idx; \ > + u64 val; \ > + int ret; \ > + \ > + ret = kstrtou64(page, 0, &val); \ > + if (ret) \ > + return ret; \ > + \ > + if (sscanf(#_name, "mw%d_offset", &win_no) != 1) \ > + return -EINVAL; \ > + \ > + idx = win_no - 1; \ > + if (idx < 0 || idx >= ntb->num_mws) { \ > + dev_err(dev, "MW%d out of range (num_mws=%d)\n", \ > + win_no, ntb->num_mws); \ > + return -EINVAL; \ > + } \ > + \ > + idx = array_index_nospec(idx, ntb->num_mws); \ > + ntb->mws_offset[idx] = val; \ > + \ > + return len; \ > +} > + > #define EPF_NTB_BAR_R(_name, _id) \ > static ssize_t epf_ntb_##_name##_show(struct config_item *item, \ > char *page) \ > @@ -1109,6 +1200,14 @@ EPF_NTB_MW_R(mw3) > EPF_NTB_MW_W(mw3) > EPF_NTB_MW_R(mw4) > EPF_NTB_MW_W(mw4) > +EPF_NTB_MW_OFF_R(mw1_offset) > +EPF_NTB_MW_OFF_W(mw1_offset) > +EPF_NTB_MW_OFF_R(mw2_offset) > +EPF_NTB_MW_OFF_W(mw2_offset) > +EPF_NTB_MW_OFF_R(mw3_offset) > +EPF_NTB_MW_OFF_W(mw3_offset) > +EPF_NTB_MW_OFF_R(mw4_offset) > +EPF_NTB_MW_OFF_W(mw4_offset) > EPF_NTB_BAR_R(ctrl_bar, BAR_CONFIG) > EPF_NTB_BAR_W(ctrl_bar, BAR_CONFIG) > EPF_NTB_BAR_R(db_bar, BAR_DB) > @@ -1129,6 +1228,10 @@ CONFIGFS_ATTR(epf_ntb_, mw1); > CONFIGFS_ATTR(epf_ntb_, mw2); > CONFIGFS_ATTR(epf_ntb_, mw3); > CONFIGFS_ATTR(epf_ntb_, mw4); > +CONFIGFS_ATTR(epf_ntb_, mw1_offset); > +CONFIGFS_ATTR(epf_ntb_, mw2_offset); > +CONFIGFS_ATTR(epf_ntb_, mw3_offset); > +CONFIGFS_ATTR(epf_ntb_, mw4_offset); > CONFIGFS_ATTR(epf_ntb_, vbus_number); > CONFIGFS_ATTR(epf_ntb_, vntb_pid); > CONFIGFS_ATTR(epf_ntb_, vntb_vid); > @@ -1147,6 +1250,10 @@ static struct configfs_attribute *epf_ntb_attrs[] = { > &epf_ntb_attr_mw2, > &epf_ntb_attr_mw3, > &epf_ntb_attr_mw4, > + &epf_ntb_attr_mw1_offset, > + &epf_ntb_attr_mw2_offset, > + &epf_ntb_attr_mw3_offset, > + &epf_ntb_attr_mw4_offset, > &epf_ntb_attr_vbus_number, > &epf_ntb_attr_vntb_pid, > &epf_ntb_attr_vntb_vid, > -- > 2.48.1 >