From: Vinod Koul <vkoul@kernel.org>
To: Devendra K Verma <devendra.verma@amd.com>
Cc: bhelgaas@google.com, mani@kernel.org, dmaengine@vger.kernel.org,
linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
michal.simek@amd.com
Subject: Re: [PATCH v7 2/2] dmaengine: dw-edma: Add non-LL mode
Date: Tue, 16 Dec 2025 18:01:36 +0530 [thread overview]
Message-ID: <aUFRKDCglF3NbNLZ@vaman> (raw)
In-Reply-To: <20251212122056.8153-3-devendra.verma@amd.com>
On 12-12-25, 17:50, Devendra K Verma wrote:
> AMD MDB IP supports Linked List (LL) mode as well as non-LL mode.
> The current code does not have the mechanisms to enable the
> DMA transactions using the non-LL mode. The following two cases
> are added with this patch:
> - For the AMD (Xilinx) only, when a valid physical base address of
> the device side DDR is not configured, then the IP can still be
> used in non-LL mode. For all the channels DMA transactions will
> be using the non-LL mode only. This, the default non-LL mode,
> is not applicable for Synopsys IP with the current code addition.
>
> - If the default mode is LL-mode, for both AMD (Xilinx) and Synosys,
> and if user wants to use non-LL mode then user can do so via
> configuring the peripheral_config param of dma_slave_config.
>
> Signed-off-by: Devendra K Verma <devendra.verma@amd.com>
> ---
> Changes in v7
> No change
>
> Changes in v6
> Gave definition to bits used for channel configuration.
> Removed the comment related to doorbell.
>
> Changes in v5
> Variable name 'nollp' changed to 'non_ll'.
> In the dw_edma_device_config() WARN_ON replaced with dev_err().
> Comments follow the 80-column guideline.
>
> Changes in v4
> No change
>
> Changes in v3
> No change
>
> Changes in v2
> Reverted the function return type to u64 for
> dw_edma_get_phys_addr().
>
> Changes in v1
> Changed the function return type for dw_edma_get_phys_addr().
> Corrected the typo raised in review.
> ---
> drivers/dma/dw-edma/dw-edma-core.c | 41 ++++++++++++++++++++---
> drivers/dma/dw-edma/dw-edma-core.h | 1 +
> drivers/dma/dw-edma/dw-edma-pcie.c | 44 +++++++++++++++++--------
> drivers/dma/dw-edma/dw-hdma-v0-core.c | 61 ++++++++++++++++++++++++++++++++++-
> drivers/dma/dw-edma/dw-hdma-v0-regs.h | 1 +
> include/linux/dma/edma.h | 1 +
> 6 files changed, 130 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/dma/dw-edma/dw-edma-core.c b/drivers/dma/dw-edma/dw-edma-core.c
> index b43255f..60a3279 100644
> --- a/drivers/dma/dw-edma/dw-edma-core.c
> +++ b/drivers/dma/dw-edma/dw-edma-core.c
> @@ -223,8 +223,31 @@ static int dw_edma_device_config(struct dma_chan *dchan,
> struct dma_slave_config *config)
> {
> struct dw_edma_chan *chan = dchan2dw_edma_chan(dchan);
> + int non_ll = 0;
> +
> + if (config->peripheral_config &&
> + config->peripheral_size != sizeof(int)) {
> + dev_err(dchan->device->dev,
> + "config param peripheral size mismatch\n");
> + return -EINVAL;
> + }
Hmm, what is this config param used for. I dont like people using this
in opaque manner. Can you explain why this needs to be passed from
client. What does non ll mean and how would client decide to use this or
not..?
--
~Vinod
next prev parent reply other threads:[~2025-12-16 12:31 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-12 12:20 [PATCH v7 0/2] Add AMD MDB Endpoint and non-LL mode Support Devendra K Verma
2025-12-12 12:20 ` [PATCH v7 1/2] dmaengine: dw-edma: Add AMD MDB Endpoint Support Devendra K Verma
2025-12-12 18:08 ` Bjorn Helgaas
2025-12-15 11:39 ` Verma, Devendra
2025-12-12 12:20 ` [PATCH v7 2/2] dmaengine: dw-edma: Add non-LL mode Devendra K Verma
2025-12-12 18:21 ` Bjorn Helgaas
2025-12-16 10:15 ` Verma, Devendra
2025-12-23 16:28 ` Bjorn Helgaas
2026-01-05 10:30 ` Verma, Devendra
2025-12-16 12:31 ` Vinod Koul [this message]
2026-01-05 10:35 ` Verma, Devendra
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