Re: [PATCH 0/5] dma: dma-axi-dmac: Add cyclic transfer support and graceful termination

[Vinod Koul <vkoul@kernel.org>]

On 27-01-26, 14:28, Nuno Sá via B4 Relay wrote:
> This series adds support for cyclic transfers in the .device_prep_peripheral_dma_vec()
> callback and implements graceful termination of cyclic transfers using the
> DMA_PREP_LOAD_EOT flag. Using DMA_PREP_REPEAT and DMA_PREP_LOAD_EOT is
> based on the discussion in [1].
> 
> Currently, the only way to stop a cyclic transfer is through brute force using
> .device_terminate_all(), which terminates all pending transfers. This series
> introduces a mechanism to gracefully terminate individual cyclic transfers when
> a new transfer flagged with DMA_PREP_LOAD_EOT is queued.
> 
> We need two different approaches:
> 
> 1. Software-managed cyclic transfers: These generate EOT (End-Of-Transfer)
>    interrupts for each cycle. Hence, termination can be handled directly
>    in the interrupt handler when the EOT interrupt fires, making the
>    transition to the next transfer straightforward.
> 
> 2. Hardware-managed cyclic transfers: These are optimized to avoid interrupt
>    overhead by suppressing EOT interrupts. Since there are no EOT interrupts,
>    termination must be detected at SOF (Start-Of-Frame) when new transfers
>    are being considered. The transfer is marked for termination and the
>    hardware is configured to end the current cycle gracefully.
> 
> For HW-managed cyclic mode, the series handles both scatter-gather and non-SG
> variants. With SG support, the last segment flags are modified to trigger EOT.
> Without SG, the CYCLIC flag is cleared to allow natural completion. A workaround
> is included for older IP cores (pre-4.6.a) that can prefetch data incorrectly
> when clearing the CYCLIC flag, requiring a core disable/enable cycle.
> 
> [1]: https://lore.kernel.org/dmaengine/ZhJW9JEqN2wrejvC@matsya/
> 
> ---
> Nuno Sá (5):
>       dmaengine: Document cyclic transfer for dmaengine_prep_peripheral_dma_vec()
>       dma: dma-axi-dmac: add cyclic transfers in .device_prep_peripheral_dma_vec()
>       dma: dma-axi-dmac: add helper for getting next desc
>       dma: dma-axi-dmac: Gracefully terminate SW cyclic transfers
>       dma: dma-axi-dmac: gracefully terminate HW cyclic transfers

Please be consistent in naming, it should dmaengine: dma-axi-dmac: xxx
everywhere!

-- 
~Vinod