From: Vinod Koul <vkoul@kernel.org>
To: Devendra K Verma <devendra.verma@amd.com>
Cc: bhelgaas@google.com, mani@kernel.org, dmaengine@vger.kernel.org,
linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
michal.simek@amd.com
Subject: Re: [PATCH v13 0/2] Add AMD MDB Endpoint and non-LL mode Support
Date: Tue, 17 Mar 2026 16:32:58 +0530 [thread overview]
Message-ID: <abk04pkF4mOR0rKP@vaman> (raw)
In-Reply-To: <20260311111834.3750297-1-devendra.verma@amd.com>
On 11-03-26, 16:48, Devendra K Verma wrote:
> This series of patch support the following:
>
> - AMD MDB Endpoint Support, as part of this patch following are
> added:
> o AMD supported device ID and vendor ID (Xilinx)
> o AMD MDB specific driver data
> o AMD specific VSEC capabilities to retrieve the base of
> phys address of MDB side DDR
> o Logic to assign the offsets to LL and data blocks if
> more number of channels are enabled than configured
> in the given pci_data struct.
>
> - Addition of non-LL mode
> o The IP supported non-LL mode functions
> o Flexibility to choose non-LL mode via dma_slave_config
> param peripheral_config, by the client for all the vendors
> using HDMA IP.
> o Allow IP utilization if LL mode is not available
There is trailing whitespace in patch2 and even then it fails for me on
dmaengine/next. Please rebase and resend
--
~Vinod
next prev parent reply other threads:[~2026-03-17 11:03 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-11 11:18 [PATCH v13 0/2] Add AMD MDB Endpoint and non-LL mode Support Devendra K Verma
2026-03-11 11:18 ` [PATCH v13 1/2] dmaengine: dw-edma: Add AMD MDB Endpoint Support Devendra K Verma
2026-03-11 11:18 ` [PATCH v13 2/2] dmaengine: dw-edma: Add non-LL mode Devendra K Verma
2026-03-17 11:02 ` Vinod Koul [this message]
2026-03-17 12:24 ` [PATCH v13 0/2] Add AMD MDB Endpoint and non-LL mode Support Verma, Devendra
2026-03-18 7:03 ` Verma, Devendra
2026-03-18 11:27 ` Vinod Koul
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