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Thank for your trying this, which I want to do long time ago. The key problem is how to guarratee safe when link to last TCD and DMA is working it? if update last TCD's next pointer before DMA load it, it is good. but, if update last TCD's next pointer after DMA load it. DMA engine may stop. how do you test it? and how much preformance improved? Frank > > Linking is only done if the last TCD was set to disable the DMA channel, > to prevent corrupting cyclic transaction. > > Update fsl_edma_xfer_desc() to avoid re-initializing the hardware when a > transfer is already in progress, allowing seamless chaining of descriptors. > > Modify the transfer completion handler to check the DONE flag in the > channel CSR before marking the transfer complete. Since this flag is > only available on SoC with the split registers layout, we only link > transactions for DMA controllers flagged with FSL_EDMA_DRV_SPLIT_REG. > > Add trace event for scatter/gather linking operations. > > Signed-off-by: Benoît Monin > --- > drivers/dma/fsl-edma-common.c | 64 ++++++++++++++++++++++++++++++++++++++++--- > drivers/dma/fsl-edma-trace.h | 5 ++++ > 2 files changed, 65 insertions(+), 4 deletions(-) > > diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c > index 26a5ecf493b9..7094c747defa 100644 > --- a/drivers/dma/fsl-edma-common.c > +++ b/drivers/dma/fsl-edma-common.c > @@ -58,7 +58,10 @@ void fsl_edma_tx_chan_handler(struct fsl_edma_chan *fsl_chan) > list_del(&fsl_chan->edesc->vdesc.node); > vchan_cookie_complete(&fsl_chan->edesc->vdesc); > fsl_chan->edesc = NULL; > - fsl_chan->status = DMA_COMPLETE; > + if (!(fsl_edma_drvflags(fsl_chan) & FSL_EDMA_DRV_SPLIT_REG) || > + (edma_readl_chreg(fsl_chan, ch_csr) & EDMA_V3_CH_CSR_DONE)) { > + fsl_chan->status = DMA_COMPLETE; > + } > } else { > vchan_cyclic_callback(&fsl_chan->edesc->vdesc); > } > @@ -673,6 +676,51 @@ struct dma_async_tx_descriptor *fsl_edma_prep_dma_cyclic( > return vchan_tx_prep(&fsl_chan->vchan, &fsl_desc->vdesc, flags); > } > > +static void fsl_edma_link_sg(struct fsl_edma_chan *fsl_chan, struct fsl_edma_desc *fsl_desc) > +{ > + u32 flags = fsl_edma_drvflags(fsl_chan); > + struct virt_dma_desc *vdesc; > + struct fsl_edma_desc *prev_desc; > + struct fsl_edma_hw_tcd *last_tcd; > + u16 csr; > + > + if (!(flags & FSL_EDMA_DRV_SPLIT_REG)) > + return; > + > + guard(spinlock_irqsave)(&fsl_chan->vchan.lock); > + > + vdesc = list_last_entry_or_null(&fsl_chan->vchan.desc_issued, > + struct virt_dma_desc, node); > + if (!vdesc) > + vdesc = list_last_entry_or_null(&fsl_chan->vchan.desc_submitted, > + struct virt_dma_desc, node); > + if (!vdesc) > + return; > + > + prev_desc = to_fsl_edma_desc(vdesc); > + last_tcd = prev_desc->tcd[prev_desc->n_tcds - 1].vtcd; > + > + csr = fsl_edma_get_tcd_to_cpu(fsl_chan, last_tcd, csr); > + if (!(csr & EDMA_TCD_CSR_D_REQ)) > + return; > + > + fsl_edma_set_tcd_to_le(fsl_chan, last_tcd, fsl_desc->tcd[0].ptcd, dlast_sga); > + > + csr &= ~EDMA_TCD_CSR_D_REQ; > + csr |= EDMA_TCD_CSR_E_SG; > + fsl_edma_set_tcd_to_le(fsl_chan, last_tcd, csr, csr); > + > + if (prev_desc == fsl_chan->edesc && prev_desc->n_tcds == 1) { > + if (flags & FSL_EDMA_DRV_CLEAR_DONE_E_SG) > + edma_writel_chreg(fsl_chan, edma_readl_chreg(fsl_chan, ch_csr), ch_csr); > + > + edma_cp_tcd_to_reg(fsl_chan, last_tcd, dlast_sga); > + edma_cp_tcd_to_reg(fsl_chan, last_tcd, csr); > + } > + > + trace_edma_link_sg(fsl_chan, last_tcd); > +} > + > struct dma_async_tx_descriptor *fsl_edma_prep_peripheral_dma_vec( > struct dma_chan *chan, const struct dma_vec *vecs, > size_t nb, enum dma_transfer_direction direction, > @@ -780,6 +828,9 @@ struct dma_async_tx_descriptor *fsl_edma_prep_peripheral_dma_vec( > } > } > > + if (!fsl_desc->iscyclic) > + fsl_edma_link_sg(fsl_chan, fsl_desc); > + > return vchan_tx_prep(&fsl_chan->vchan, &fsl_desc->vdesc, flags); > } > > @@ -883,6 +934,8 @@ struct dma_async_tx_descriptor *fsl_edma_prep_slave_sg( > } > } > > + fsl_edma_link_sg(fsl_chan, fsl_desc); > + > return vchan_tx_prep(&fsl_chan->vchan, &fsl_desc->vdesc, flags); > } > > @@ -925,9 +978,12 @@ void fsl_edma_xfer_desc(struct fsl_edma_chan *fsl_chan) > if (!vdesc) > return; > fsl_chan->edesc = to_fsl_edma_desc(vdesc); > - fsl_edma_set_tcd_regs(fsl_chan, fsl_chan->edesc->tcd[0].vtcd); > - fsl_edma_enable_request(fsl_chan); > - fsl_chan->status = DMA_IN_PROGRESS; > + > + if (fsl_chan->status != DMA_IN_PROGRESS) { > + fsl_edma_set_tcd_regs(fsl_chan, fsl_chan->edesc->tcd[0].vtcd); > + fsl_edma_enable_request(fsl_chan); > + fsl_chan->status = DMA_IN_PROGRESS; > + } > } > > void fsl_edma_issue_pending(struct dma_chan *chan) > diff --git a/drivers/dma/fsl-edma-trace.h b/drivers/dma/fsl-edma-trace.h > index d3541301a247..ac319d2dbb90 100644 > --- a/drivers/dma/fsl-edma-trace.h > +++ b/drivers/dma/fsl-edma-trace.h > @@ -119,6 +119,11 @@ DEFINE_EVENT(edma_log_tcd, edma_fill_tcd, > TP_ARGS(chan, tcd) > ); > > +DEFINE_EVENT(edma_log_tcd, edma_link_sg, > + TP_PROTO(struct fsl_edma_chan *chan, void *tcd), > + TP_ARGS(chan, tcd) > +); > + > #endif > > /* this part must be outside header guard */ > > -- > 2.54.0 >