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DMA engine > > may stop. > > > I followed what is described in the dynamic scatter/gather chapter of the > i.MX93 reference manual. We update two registers of the last TCD when > chaining SG transfers, first TCD_DLAST_SGA then TCD_CSR. This gives us > three possibilities of concurrence between CPU writes and eDMA reads. > > * First case, both registers are updated before the eDMA reads the TCD, we > get the expected chaining. > * Second case, both registers are updated too late and the eDMA have already > read the TCD, we are back to the current implementation. After processing > the last TCD, the eDMA will disable the channel and the call to > fsl_edma_xfer_desc() from fsl_edma_tx_chan_handler() will move to the next > issued descriptor and re-enable the channel. > * Final case, only TCD_DLAST_SGA gets picked up by the eDMA. The eDMA will > also disable the channel after processing the last TCD, the only difference > is that it will update TCD_DADDR by adding the value TCD_DLAST_SGA. Since > we are not reusing TCD_DADDR, this has no impact. Okay, possible work, let me think more detail after you remove RFC. > > > how do you test it? and how much preformance improved? > I did my tests by doing SPI transfers with the LPSPI controllers, doing DMA > transactions with different number of buffers and different buffer sizes. > Without chaining, interruptions on the SPI bus occur between each DMA > transaction. With chaining, the activity on the SPI bus is continuous as > long as DMA transactions are issued before the end of the current > transaction. Does SPI support issue new transfers without wait for previous transfer complete, or SPI transfer already support async queue? Frank > > Best regards, > -- > Benoît Monin, Bootlin > Embedded Linux and Kernel engineering > https://bootlin.com > > >