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Not sure there's anything to be fixed in > > > > > there... The code seems to use the dma bus width to match against PCM > > > > > formats supported and filter only the ones we can support (per dma cap). > > > > > > > > if cap is one byte, it should support 8, 16, 24, 32, 64 > > > > if cap is two byte, it should support 16, 32, 64 > > > > if cap is 4 byte, it only support 32 and 64. > > > > > > Well, Now I see your point but not exactly. Because we do have > > > > > > DMA_SLAVE_BUSWIDTH_3_BYTES > > > > > > and it might be used by the pcm_dmaengine code, > > > > > > There are also some controllers that set it. But it looks like all that > > > set it also set 1byte. > > > > But this might be not true for all HW in the world. In previous reply I made > > a comparison with MMIO accesses where not all HW that needs 1-byte read can > > cope with that. If there is some proof that this is the case when 1-byte > > DMA bus implies 3-bytes (or other odd number), I would like to see it. > > True. I'm also not too keen in making the above assumption and have no > proof that it will work for the controllers we support. Okay, I think it is fine by use bitmask. suggest change name to src_bus_widths, addr_wdiths is quite confused. And since not much place use it. suggest change all consumers and cleanup original u32 src_addr_widths in followup patches. Frank > > - Nuno Sá > > > > > > So your suggestion might still hold and work but I'm not too convinced > > > that having the array complicates things that bad when compared with the > > > risk of breaking existing code. > > > > > > Needn't mask each bit. > > > > -- > > With Best Regards, > > Andy Shevchenko > > > >